From: Jisheng Zhang <jszhang@marvell.com>
To: Joao Pinto <Joao.Pinto@synopsys.com>,
Jingoo Han <jingoohan1@gmail.com>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [RFC] PCI: dwc: designware: allow customize unroll registers' readl/writel
Date: Thu, 13 Jul 2017 18:52:13 +0800 [thread overview]
Message-ID: <20170713185213.0b04a4fc@xhacker> (raw)
In-Reply-To: <20170713184837.541ccf26@xhacker>
On Thu, 13 Jul 2017 18:48:37 +0800 Jisheng Zhang wrote:
> Hi Joao, Jingoo,
>
> Now, the PCIE_GET_ATU_OUTB_UNR_REG_OFFSET macro is defined as:
>
> /* Register address builder */
> #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
> ((0x3 << 20) | ((region) << 9))
>
> I have one question: where does the (0x3 << 20) come from? 2MB space, a bit
sorry, typo. (0x3 << 20) should be 3MB.
> large. And I didn't find it in the databook. Is it platform specific?
> If yes, I want to cook one patch to customize unroll registers' readl/writel.
>
> And how does (0x3 << 20) enable DBI2 access?
>
> Thanks in advance,
> Jisheng
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WARNING: multiple messages have this Message-ID (diff)
From: jszhang@marvell.com (Jisheng Zhang)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC] PCI: dwc: designware: allow customize unroll registers' readl/writel
Date: Thu, 13 Jul 2017 18:52:13 +0800 [thread overview]
Message-ID: <20170713185213.0b04a4fc@xhacker> (raw)
In-Reply-To: <20170713184837.541ccf26@xhacker>
On Thu, 13 Jul 2017 18:48:37 +0800 Jisheng Zhang wrote:
> Hi Joao, Jingoo,
>
> Now, the PCIE_GET_ATU_OUTB_UNR_REG_OFFSET macro is defined as:
>
> /* Register address builder */
> #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
> ((0x3 << 20) | ((region) << 9))
>
> I have one question: where does the (0x3 << 20) come from? 2MB space, a bit
sorry, typo. (0x3 << 20) should be 3MB.
> large. And I didn't find it in the databook. Is it platform specific?
> If yes, I want to cook one patch to customize unroll registers' readl/writel.
>
> And how does (0x3 << 20) enable DBI2 access?
>
> Thanks in advance,
> Jisheng
next prev parent reply other threads:[~2017-07-13 10:52 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-13 10:48 [RFC] PCI: dwc: designware: allow customize unroll registers' readl/writel Jisheng Zhang
2017-07-13 10:48 ` Jisheng Zhang
2017-07-13 10:52 ` Jisheng Zhang [this message]
2017-07-13 10:52 ` Jisheng Zhang
2017-07-17 8:59 ` Joao Pinto
2017-07-17 8:59 ` Joao Pinto
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