* [PATCH] clk: renesas: rcar-gen3: Fix SD divider setting
@ 2017-04-19 17:46 Yoshihiro Kaneko
2017-07-21 20:16 ` Stephen Boyd
0 siblings, 1 reply; 5+ messages in thread
From: Yoshihiro Kaneko @ 2017-04-19 17:46 UTC (permalink / raw)
To: linux-clk
Cc: Michael Turquette, Stephen Boyd, Geert Uytterhoeven, Simon Horman,
Magnus Damm, linux-renesas-soc
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
This patch fixed the SD divider settiing for corresponding to the change
in the HS200/HS400 mode.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---
This patch is based on the clk-next branch of linux-clk tree.
drivers/clk/renesas/rcar-gen3-cpg.c | 41 +++++++++++++++++++------------------
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 8419f27..4ab76b1 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -1,6 +1,7 @@
/*
* R-Car Gen3 Clock Pulse Generator
*
+ * Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2015-2016 Glider bvba
*
* Based on clk-rcar-gen3.c
@@ -205,29 +206,29 @@ struct sd_clock {
* sd_srcfc sd_fc div
* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
*-------------------------------------------------------------------
- * 0 0 0 (1) 1 (4) 4
- * 0 0 1 (2) 1 (4) 8
- * 1 0 2 (4) 1 (4) 16
- * 1 0 3 (8) 1 (4) 32
- * 1 0 4 (16) 1 (4) 64
- * 0 0 0 (1) 0 (2) 2
- * 0 0 1 (2) 0 (2) 4
- * 1 0 2 (4) 0 (2) 8
- * 1 0 3 (8) 0 (2) 16
- * 1 0 4 (16) 0 (2) 32
+ * 0 0 1 (2) 0 (-) 2 : HS400
+ * 0 0 0 (1) 1 (4) 4 : SDR104 / HS200
+ * 0 0 1 (2) 1 (4) 8 : SDR50
+ * 1 0 2 (4) 1 (4) 16 : HS / SDR25
+ * 1 0 3 (8) 1 (4) 32 : NS / SDR12
+ * 0 0 0 (1) 0 (2) 2 : (no case)
+ * 1 0 2 (4) 0 (2) 8 : (no case)
+ * 1 0 3 (8) 0 (2) 16 : (no case)
+ * 1 0 4 (16) 0 (2) 32 : (no case)
+ * 1 0 4 (16) 1 (4) 64 : (no case)
*/
static const struct sd_div_table cpg_sd_div_table[] = {
/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
- CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
- CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
- CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
- CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
- CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
- CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
- CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
- CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
- CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
- CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
+ CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 2),
+ CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
+ CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
+ CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
+ CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
+ CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
+ CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
+ CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
+ CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
+ CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
};
#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] clk: renesas: rcar-gen3: Fix SD divider setting
2017-04-19 17:46 [PATCH] clk: renesas: rcar-gen3: Fix SD divider setting Yoshihiro Kaneko
@ 2017-07-21 20:16 ` Stephen Boyd
2017-08-16 7:56 ` Geert Uytterhoeven
0 siblings, 1 reply; 5+ messages in thread
From: Stephen Boyd @ 2017-07-21 20:16 UTC (permalink / raw)
To: Yoshihiro Kaneko
Cc: linux-clk, Michael Turquette, Geert Uytterhoeven, Simon Horman,
Magnus Damm, linux-renesas-soc
On 04/20, Yoshihiro Kaneko wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch fixed the SD divider settiing for corresponding to the change
> in the HS200/HS400 mode.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> ---
> This patch is based on the clk-next branch of linux-clk tree.
Geert?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] clk: renesas: rcar-gen3: Fix SD divider setting
2017-07-21 20:16 ` Stephen Boyd
@ 2017-08-16 7:56 ` Geert Uytterhoeven
0 siblings, 0 replies; 5+ messages in thread
From: Geert Uytterhoeven @ 2017-08-16 7:56 UTC (permalink / raw)
To: Stephen Boyd
Cc: Yoshihiro Kaneko, linux-clk, Michael Turquette,
Geert Uytterhoeven, Simon Horman, Magnus Damm, Linux-Renesas,
Wolfram Sang
Hi Stephen,
On Fri, Jul 21, 2017 at 10:16 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 04/20, Yoshihiro Kaneko wrote:
>> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>
>> This patch fixed the SD divider settiing for corresponding to the change
>> in the HS200/HS400 mode.
>>
>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
>> ---
>> This patch is based on the clk-next branch of linux-clk tree.
>
> Geert?
This patch was superseded by Wolfram's series "[PATCH 0/3] clk: renesas:
rcar-gen3-cpg: updates to SD divider table", which he retracted after noticing
issues on some SoCs.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] clk: renesas: rcar-gen3: Fix SD divider setting
@ 2018-01-19 13:38 Simon Horman
2018-02-21 20:46 ` Wolfram Sang
0 siblings, 1 reply; 5+ messages in thread
From: Simon Horman @ 2018-01-19 13:38 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Magnus Damm, linux-renesas-soc, linux-clk
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
This patch fixed the SD divider settiing for corresponding to the change
in the HS200/HS400 mode.
NOTE:
- In H3/M3, the clock in HS400 mode refers to SDnH clock
(others are SDn clock). Therefore, only the division value of SD is set
as struct sd_div_table.div of cpg_sd_div_table[].
- In M3N, HS400 mode and HS200 mode use the same clock setting.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
Based on renesas-drivers/clk-renesas-for-v4.17
I believe that this is a pre-requisite for enabling HS400 as with HS400
enabled but without this patch I see:
* M3-W ES1.0 / Salvator-X
[ 1.874323] renesas_sdhi_internal_dmac ee140000.sd: mmc0 base at 0xee140000 max clock rate 200 MHz
[ 2.064014] mmc0: new HS400 MMC card at address 0001
[ 2.065225] mmcblk0: mmc0:0001 eMMC 28.8 GiB
[ 2.065722] mmcblk0boot0: mmc0:0001 eMMC partition 1 4.00 MiB
[ 2.066116] mmcblk0boot1: mmc0:0001 eMMC partition 2 4.00 MiB
[ 2.066751] mmcblk0rpmb: mmc0:0001 eMMC partition 3 4.00 MiB, chardev (243:0)
[ 2.469721] print_req_error: I/O error, dev mmcblk0, sector 0
[ 2.478455] Buffer I/O error on dev mmcblk0, logical block 0, async page read
[ 2.611630] print_req_error: I/O error, dev mmcblk0, sector 0
[ 2.613261] Buffer I/O error on dev mmcblk0, logical block 0, async page read
[ 2.623928] mmcblk0: unable to read partition table
[ 11.379974] print_req_error: I/O error, dev mmcblk0, sector 0
[ 11.477670] print_req_error: I/O error, dev mmcblk0, sector 0
[ 11.487071] Buffer I/O error on dev mmcblk0, logical block 0, async page read
[ 12.125520] print_req_error: I/O error, dev mmcblk0boot1, sector 7936
[ 12.355220] print_req_error: I/O error, dev mmcblk0boot1, sector 7936
[ 12.365142] Buffer I/O error on dev mmcblk0boot1, logical block 992, async page read
* On H3 ES2.0 / Salvator-XS:
[ 2.456253] renesas_sdhi_internal_dmac ee100000.sd: Got CD GPIO
[ 2.462243] renesas_sdhi_internal_dmac ee100000.sd: Got WP GPIO
[ 2.517855] renesas_sdhi_internal_dmac ee140000.sd: mmc0 base at 0xee140000 max clock rate 200 MHz
[ 2.527651] renesas_sdhi_internal_dmac ee160000.sd: Got CD GPIO
[ 2.533834] renesas_sdhi_internal_dmac ee160000.sd: Got WP GPIO
[ 2.645783] mmc0: error -84 whilst initialising MMC card
[ 2.745795] mmc0: error -84 whilst initialising MMC card
[ 2.894756] mmc0: error -84 whilst initialising MMC card
[ 2.957199] renesas_sdhi_internal_dmac ee100000.sd: Got CD GPIO
[ 2.964230] renesas_sdhi_internal_dmac ee100000.sd: Got WP GPIO
[ 3.020456] renesas_sdhi_internal_dmac ee100000.sd: mmc1 base at 0xee100000 max clock rate 200 MHz
[ 3.031186] renesas_sdhi_internal_dmac ee160000.sd: Got CD GPIO
[ 3.038196] renesas_sdhi_internal_dmac ee160000.sd: Got WP GPIO
[ 3.090806] renesas_sdhi_internal_dmac ee160000.sd: mmc2 base at 0xee160000 max clock rate 200 MHz
[ 3.124870] mmc0: error -84 whilst initialising MMC card
On H3 ES1.0 / Salvator-X I do not see any problems either with or without
this patch.
To assist testing and review I will make patches, including this one, to
enable HS400 on H3 / Salvator-X, M3-W 1.0 / Salvator-X and
H3 ES2.0 Salvator-XS available at:
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git topic/hs400-v2
---
drivers/clk/renesas/rcar-gen3-cpg.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 0904886f5501..caa39d33726a 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -95,32 +95,32 @@ struct sd_clock {
};
/* SDn divider
- * sd_srcfc sd_fc div
- * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
+ * sd_srcfc sd_fc div
+ * stp_hck stp_ck (div) (div) = sd_srcfc div x sd_fc div
*-------------------------------------------------------------------
- * 0 0 0 (1) 1 (4) 4
- * 0 0 1 (2) 1 (4) 8
- * 1 0 2 (4) 1 (4) 16
- * 1 0 3 (8) 1 (4) 32
- * 1 0 4 (16) 1 (4) 64
- * 0 0 0 (1) 0 (2) 2
- * 0 0 1 (2) 0 (2) 4
- * 1 0 2 (4) 0 (2) 8
- * 1 0 3 (8) 0 (2) 16
- * 1 0 4 (16) 0 (2) 32
+ * 0 0 1 (2) 0 (no refs) 2 : HS400 (H3/M3)
+ * 0 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (M3N)
+ * 0 0 1 (2) 1 (4) 8 : SDR50
+ * 1 0 2 (4) 1 (4) 16 : HS / SDR25
+ * 1 0 3 (8) 1 (4) 32 : NS / SDR12
+ * 0 0 0 (1) 0 (2) 2 : (no case)
+ * 1 0 2 (4) 0 (2) 8 : (no case)
+ * 1 0 3 (8) 0 (2) 16 : (no case)
+ * 1 0 4 (16) 0 (2) 32 : (no case)
+ * 1 0 4 (16) 1 (4) 64 : (no case)
*/
static const struct sd_div_table cpg_sd_div_table[] = {
/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
+ CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 2),
CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
- CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
- CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
+ CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
};
#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
--
2.11.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] clk: renesas: rcar-gen3: Fix SD divider setting
2018-01-19 13:38 Simon Horman
@ 2018-02-21 20:46 ` Wolfram Sang
0 siblings, 0 replies; 5+ messages in thread
From: Wolfram Sang @ 2018-02-21 20:46 UTC (permalink / raw)
To: Simon Horman
Cc: Geert Uytterhoeven, Magnus Damm, linux-renesas-soc, linux-clk
[-- Attachment #1: Type: text/plain, Size: 883 bytes --]
Simon,
sorry for the delay in checking this. I refreshed my memory about the
issues here this evening and will be able to do educated tests tomorrow.
However, one question already:
> - In M3N, HS400 mode and HS200 mode use the same clock setting.
a) I did not find any code handling this speciality for M3N, neither
here nor in the SDHI driver. Did you notice something in the BSP?
b) do you know the reasons for this? Looking at the datasheet I have,
sdsrc is 800MHz for all Gen3 SoC.
> On H3 ES1.0 / Salvator-X I do not see any problems either with or without
> this patch.
I assume this is because the speed is 200MHz instead of 400MHz. The
sdsrc clk is half speed on Salvator-X-H3-ES1.0. I hope I can confirm my
assumption tomorrow.
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git topic/hs400-v2
Thanks, that was useful!
Regards,
Wolfram
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-02-21 20:46 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-04-19 17:46 [PATCH] clk: renesas: rcar-gen3: Fix SD divider setting Yoshihiro Kaneko
2017-07-21 20:16 ` Stephen Boyd
2017-08-16 7:56 ` Geert Uytterhoeven
-- strict thread matches above, loose matches on Subject: below --
2018-01-19 13:38 Simon Horman
2018-02-21 20:46 ` Wolfram Sang
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.