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From: Stephen Boyd <sboyd@codeaurora.org>
To: Quentin Schulz <quentin.schulz@free-electrons.com>
Cc: mturquette@baylibre.com, robh+dt@kernel.org,
	mark.rutland@arm.com, lgirdwood@gmail.com, broonie@kernel.org,
	nicolas.ferre@microchip.com,
	alexandre.belloni@free-electrons.com, linux@armlinux.org.uk,
	boris.brezillon@free-electrons.com, perex@perex.cz,
	tiwai@suse.com, cyrille.pitchen@wedev4u.fr,
	thomas.petazzoni@free-electrons.com, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	alsa-devel@alsa-project.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 2/9] clk: at91: add audio plls to the compatible list in DT binding
Date: Fri, 21 Jul 2017 15:21:06 -0700	[thread overview]
Message-ID: <20170721222106.GP19878@codeaurora.org> (raw)
In-Reply-To: <20170713074927.10882-3-quentin.schulz@free-electrons.com>

On 07/13, Quentin Schulz wrote:
> This new clock driver set allows to have a fractional divided clock that
> would generate a precise clock particularly suitable for audio
> applications.
> 
> The main audio pll clock has two children clocks: one that is connected
> to the PMC, the other that can directly drive a pad. As these two routes
> have different enable bits and different dividers and divider formulas,
> they are handled by two different drivers.
> 
> This adds the audio plls (frac, pad and pmc) to the compatible list of
> at91 clocks in DT binding.
> 
> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> 
> added in v2:
>   - split from big patch with pll drivers and dt-binding

Subject seems wrong. Should have "bindings" somewhere?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/9] clk: at91: add audio plls to the compatible list in DT binding
Date: Fri, 21 Jul 2017 15:21:06 -0700	[thread overview]
Message-ID: <20170721222106.GP19878@codeaurora.org> (raw)
In-Reply-To: <20170713074927.10882-3-quentin.schulz@free-electrons.com>

On 07/13, Quentin Schulz wrote:
> This new clock driver set allows to have a fractional divided clock that
> would generate a precise clock particularly suitable for audio
> applications.
> 
> The main audio pll clock has two children clocks: one that is connected
> to the PMC, the other that can directly drive a pad. As these two routes
> have different enable bits and different dividers and divider formulas,
> they are handled by two different drivers.
> 
> This adds the audio plls (frac, pad and pmc) to the compatible list of
> at91 clocks in DT binding.
> 
> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> 
> added in v2:
>   - split from big patch with pll drivers and dt-binding

Subject seems wrong. Should have "bindings" somewhere?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

  parent reply	other threads:[~2017-07-21 22:21 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-13  7:49 [PATCH v3 0/9] add support for Sama5d2 audio PLLs and enable ClassD Quentin Schulz
2017-07-13  7:49 ` Quentin Schulz
2017-07-13  7:49 ` [PATCH v3 1/9] clk: at91: clk-generated: remove useless divisor loop Quentin Schulz
2017-07-13  7:49   ` Quentin Schulz
2017-07-13  7:49   ` Quentin Schulz
2017-07-13  7:49 ` [PATCH v3 2/9] clk: at91: add audio plls to the compatible list in DT binding Quentin Schulz
2017-07-13  7:49   ` Quentin Schulz
     [not found]   ` <20170713074927.10882-3-quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-07-19  6:31     ` Boris Brezillon
2017-07-19  6:31       ` Boris Brezillon
2017-07-19  6:31       ` Boris Brezillon
2017-07-21 22:21   ` Stephen Boyd [this message]
2017-07-21 22:21     ` Stephen Boyd
2017-07-13  7:49 ` [PATCH v3 3/9] clk: at91: add audio pll clock drivers Quentin Schulz
2017-07-13  7:49   ` Quentin Schulz
2017-07-13  7:49   ` Quentin Schulz
2017-07-19  6:31   ` Boris Brezillon
2017-07-19  6:31     ` Boris Brezillon
     [not found]   ` <20170713074927.10882-4-quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-07-21 22:20     ` Stephen Boyd
2017-07-21 22:20       ` Stephen Boyd
2017-07-21 22:20       ` Stephen Boyd
     [not found]       ` <20170721222029.GO19878-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-24  8:37         ` Quentin Schulz
2017-07-24  8:37           ` Quentin Schulz
2017-07-24  8:37           ` Quentin Schulz
     [not found]           ` <859d2f48-a987-afda-1e9d-02930e4fad7d-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-07-26  0:20             ` Stephen Boyd
2017-07-26  0:20               ` Stephen Boyd
2017-07-26  0:20               ` Stephen Boyd
2017-07-25 11:30       ` Quentin Schulz
2017-07-25 11:30         ` Quentin Schulz
2017-07-26  0:14         ` Stephen Boyd
2017-07-26  0:14           ` Stephen Boyd
2017-07-13  7:49 ` [PATCH v3 4/9] ARM: dts: at91: sama5d2: add classd nodes Quentin Schulz
2017-07-13  7:49   ` Quentin Schulz
2017-07-13  7:49   ` Quentin Schulz
2017-07-13  7:49 ` [PATCH v3 5/9] clk: at91: clk-generated: create function to find best_diff Quentin Schulz
2017-07-13  7:49   ` Quentin Schulz
2017-07-13  7:49 ` [PATCH v3 6/9] clk: at91: clk-generated: make gclk determine audio_pll rate Quentin Schulz
2017-07-13  7:49   ` Quentin Schulz
2017-07-13  7:49   ` Quentin Schulz
2017-07-13  7:49 ` [PATCH v3 7/9] ASoC: atmel-classd: remove aclk clock from DT binding Quentin Schulz
2017-07-13  7:49   ` Quentin Schulz
2017-07-13  7:49   ` Quentin Schulz
2017-07-13  7:49 ` [PATCH v3 8/9] ASoC: atmel-classd: remove aclk clock Quentin Schulz
2017-07-13  7:49   ` Quentin Schulz
2017-07-13  7:49 ` [PATCH v3 9/9] ARM: dts: at91: sama5d2_xplained: add pin muxing and enable classd Quentin Schulz
2017-07-13  7:49   ` Quentin Schulz
2017-07-19  6:28 ` [PATCH v3 0/9] add support for Sama5d2 audio PLLs and enable ClassD Quentin Schulz
2017-07-19  6:28   ` Quentin Schulz
2017-07-19 10:19   ` Mark Brown
2017-07-19 10:19     ` Mark Brown

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