All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH v1] perf: cs-etm: Fix ETMv4 CONFIGR entry in perf.data file
@ 2017-07-12 17:01 Mike Leach
  2017-07-17 15:11 ` Mathieu Poirier
  2017-07-21 14:50 ` Mathieu Poirier
  0 siblings, 2 replies; 10+ messages in thread
From: Mike Leach @ 2017-07-12 17:01 UTC (permalink / raw)
  To: linux-arm-kernel

The value passed into the perf.data file for the CONFIGR register in ETMv4
was incorrectly being set to the command line options/ETMv3 value.

Adds bit definitions and function to remap this value to the correct ETMv4
CONFIGR bit values for all selected options.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
---
Changes for v1:
 - Added more people to the recipient list.

 include/linux/coresight-pmu.h       |  5 +++++
 tools/include/linux/coresight-pmu.h |  5 +++++
 tools/perf/arch/arm/util/cs-etm.c   | 28 +++++++++++++++++++++++++++-
 3 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
index 45852c2..edfeaba 100644
--- a/include/linux/coresight-pmu.h
+++ b/include/linux/coresight-pmu.h
@@ -26,6 +26,11 @@
 #define ETM_OPT_TS      28
 #define ETM_OPT_RETSTK	29
 
+/* ETMv4 CONFIGR programming bits for the ETM OPTs */
+#define ETM4_CFG_BIT_CYCACC	4
+#define ETM4_CFG_BIT_TS		11
+#define ETM4_CFG_BIT_RETSTK	12
+
 static inline int coresight_get_trace_id(int cpu)
 {
 	/*
diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h
index 45852c2..edfeaba 100644
--- a/tools/include/linux/coresight-pmu.h
+++ b/tools/include/linux/coresight-pmu.h
@@ -26,6 +26,11 @@
 #define ETM_OPT_TS      28
 #define ETM_OPT_RETSTK	29
 
+/* ETMv4 CONFIGR programming bits for the ETM OPTs */
+#define ETM4_CFG_BIT_CYCACC	4
+#define ETM4_CFG_BIT_TS		11
+#define ETM4_CFG_BIT_RETSTK	12
+
 static inline int coresight_get_trace_id(int cpu)
 {
 	/*
diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c
index 29361d9..997734b 100644
--- a/tools/perf/arch/arm/util/cs-etm.c
+++ b/tools/perf/arch/arm/util/cs-etm.c
@@ -266,6 +266,32 @@ static u64 cs_etm_get_config(struct auxtrace_record *itr)
 	return config;
 }
 
+#ifndef BIT
+#define BIT(N) (1UL << (N))
+#endif
+
+static u64 cs_etmv4_get_config(struct auxtrace_record *itr)
+{
+	u64 config = 0;
+	u64 config_opts = 0;
+
+	/*
+	 * The perf event variable config bits represent both
+	 * the command line options and register programming
+	 * bits in ETMv3/PTM. For ETMv4 we must remap options
+	 * to real bits
+	 */
+	config_opts = cs_etm_get_config(itr);
+	if (config_opts & BIT(ETM_OPT_CYCACC))
+		config |= BIT(ETM4_CFG_BIT_CYCACC);
+	if (config_opts & BIT(ETM_OPT_TS))
+		config |= BIT(ETM4_CFG_BIT_TS);
+	if (config_opts & BIT(ETM_OPT_RETSTK))
+		config |= BIT(ETM4_CFG_BIT_RETSTK);
+
+	return config;
+}
+
 static size_t
 cs_etm_info_priv_size(struct auxtrace_record *itr __maybe_unused,
 		      struct perf_evlist *evlist __maybe_unused)
@@ -363,7 +389,7 @@ static void cs_etm_get_metadata(int cpu, u32 *offset,
 		magic = __perf_cs_etmv4_magic;
 		/* Get trace configuration register */
 		info->priv[*offset + CS_ETMV4_TRCCONFIGR] =
-						cs_etm_get_config(itr);
+						cs_etmv4_get_config(itr);
 		/* Get traceID from the framework */
 		info->priv[*offset + CS_ETMV4_TRCTRACEIDR] =
 						coresight_get_trace_id(cpu);
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2017-08-01 16:44 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-07-12 17:01 [PATCH v1] perf: cs-etm: Fix ETMv4 CONFIGR entry in perf.data file Mike Leach
2017-07-17 15:11 ` Mathieu Poirier
2017-07-21 14:50 ` Mathieu Poirier
2017-07-21 16:19   ` Arnaldo Carvalho de Melo
2017-07-21 18:35     ` Arnaldo Carvalho de Melo
2017-07-21 18:37       ` Arnaldo Carvalho de Melo
2017-07-21 19:11         ` Arnaldo Carvalho de Melo
2017-07-24 19:37           ` Mathieu Poirier
2017-08-01 16:17             ` Mathieu Poirier
2017-08-01 16:44               ` Arnaldo Carvalho de Melo

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.