* [PATCH 1/2] drm/i915/cnl: simplify cnl_procmon_values handling
@ 2017-08-22 0:03 Rodrigo Vivi
2017-08-22 0:03 ` [PATCH 2/2] drm/i915/cnl: extract cnl_set_procmon_ref_values Rodrigo Vivi
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Rodrigo Vivi @ 2017-08-22 0:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Make it a little less magical and a little simpler and more hardcoded
so we don't end up with an array that's composed mostly of empty
entries.
v2: Add an enum for the voltage+register values (Ville).
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 58 +++++++++++++++++++++------------
1 file changed, 37 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b66d8e136aa3..b7f4fbe7ae0d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2707,24 +2707,27 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
usleep_range(10, 30); /* 10 us delay per Bspec */
}
-#define CNL_PROCMON_IDX(val) \
- (((val) & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) >> VOLTAGE_INFO_SHIFT)
-#define NUM_CNL_PROCMON \
- (CNL_PROCMON_IDX(VOLTAGE_INFO_MASK | PROCESS_INFO_MASK) + 1)
+enum {
+ PROCMON_0_85V_DOT_0,
+ PROCMON_0_95V_DOT_0,
+ PROCMON_0_95V_DOT_1,
+ PROCMON_1_05V_DOT_0,
+ PROCMON_1_05V_DOT_1,
+};
static const struct cnl_procmon {
u32 dw1, dw9, dw10;
-} cnl_procmon_values[NUM_CNL_PROCMON] = {
- [CNL_PROCMON_IDX(VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0)] =
- { .dw1 = 0x00 << 16, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
- [CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0)] =
- { .dw1 = 0x00 << 16, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
- [CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1)] =
- { .dw1 = 0x00 << 16, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
- [CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0)] =
- { .dw1 = 0x00 << 16, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
- [CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1)] =
- { .dw1 = 0x44 << 16, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
+} cnl_procmon_values[] = {
+ [PROCMON_0_85V_DOT_0] =
+ { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
+ [PROCMON_0_95V_DOT_0] =
+ { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
+ [PROCMON_0_95V_DOT_1] =
+ { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
+ [PROCMON_1_05V_DOT_0] =
+ { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
+ [PROCMON_1_05V_DOT_1] =
+ { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
};
static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
@@ -2747,9 +2750,25 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
I915_WRITE(CHICKEN_MISC_2, val);
val = I915_READ(CNL_PORT_COMP_DW3);
- procmon = &cnl_procmon_values[CNL_PROCMON_IDX(val)];
-
- WARN_ON(procmon->dw10 == 0);
+ switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
+ default:
+ MISSING_CASE(val);
+ case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
+ procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
+ break;
+ case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
+ procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
+ break;
+ case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
+ procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
+ break;
+ case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
+ procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
+ break;
+ case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
+ procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
+ break;
+ }
val = I915_READ(CNL_PORT_COMP_DW1);
val &= ~((0xff << 16) | 0xff);
@@ -2784,9 +2803,6 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
gen9_dbuf_enable(dev_priv);
}
-#undef CNL_PROCMON_IDX
-#undef NUM_CNL_PROCMON
-
static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
--
2.13.2
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/2] drm/i915/cnl: extract cnl_set_procmon_ref_values
2017-08-22 0:03 [PATCH 1/2] drm/i915/cnl: simplify cnl_procmon_values handling Rodrigo Vivi
@ 2017-08-22 0:03 ` Rodrigo Vivi
2017-08-22 0:46 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: simplify cnl_procmon_values handling Patchwork
2017-08-22 14:44 ` [PATCH 1/2] " Ville Syrjälä
2 siblings, 0 replies; 5+ messages in thread
From: Rodrigo Vivi @ 2017-08-22 0:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Move the part that reads the table and sets registers based on the
table to its own function.
v2: Rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 37 ++++++++++++++++++++-------------
1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b7f4fbe7ae0d..a3bfb9f27e7a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2730,25 +2730,11 @@ static const struct cnl_procmon {
{ .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
};
-static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
+static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
const struct cnl_procmon *procmon;
- struct i915_power_well *well;
u32 val;
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
-
- /* 1. Enable PCH Reset Handshake */
- val = I915_READ(HSW_NDE_RSTWRN_OPT);
- val |= RESET_PCH_HANDSHAKE_ENABLE;
- I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
-
- /* 2. Enable Comp */
- val = I915_READ(CHICKEN_MISC_2);
- val &= ~CNL_COMP_PWR_DOWN;
- I915_WRITE(CHICKEN_MISC_2, val);
-
val = I915_READ(CNL_PORT_COMP_DW3);
switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
default:
@@ -2777,6 +2763,27 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
+}
+
+static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
+{
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_well *well;
+ u32 val;
+
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+ /* 1. Enable PCH Reset Handshake */
+ val = I915_READ(HSW_NDE_RSTWRN_OPT);
+ val |= RESET_PCH_HANDSHAKE_ENABLE;
+ I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+
+ /* 2. Enable Comp */
+ val = I915_READ(CHICKEN_MISC_2);
+ val &= ~CNL_COMP_PWR_DOWN;
+ I915_WRITE(CHICKEN_MISC_2, val);
+
+ cnl_set_procmon_ref_values(dev_priv);
val = I915_READ(CNL_PORT_COMP_DW0);
val |= COMP_INIT;
--
2.13.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: simplify cnl_procmon_values handling
2017-08-22 0:03 [PATCH 1/2] drm/i915/cnl: simplify cnl_procmon_values handling Rodrigo Vivi
2017-08-22 0:03 ` [PATCH 2/2] drm/i915/cnl: extract cnl_set_procmon_ref_values Rodrigo Vivi
@ 2017-08-22 0:46 ` Patchwork
2017-08-22 14:44 ` [PATCH 1/2] " Ville Syrjälä
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-08-22 0:46 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/cnl: simplify cnl_procmon_values handling
URL : https://patchwork.freedesktop.org/series/29115/
State : success
== Summary ==
Series 29115v1 series starting with [1/2] drm/i915/cnl: simplify cnl_procmon_values handling
https://patchwork.freedesktop.org/api/1.0/series/29115/revisions/1/mbox/
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:457s
fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:442s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:363s
fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:553s
fi-bwr-2160 total:279 pass:184 dwarn:0 dfail:0 fail:0 skip:95 time:253s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:523s
fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:526s
fi-byt-n2820 total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:518s
fi-elk-e7500 total:279 pass:230 dwarn:0 dfail:0 fail:0 skip:49 time:432s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:609s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:450s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:424s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:421s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:506s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:474s
fi-kbl-7260u total:279 pass:268 dwarn:1 dfail:0 fail:0 skip:10 time:501s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:477s
fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:593s
fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:604s
fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:527s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:470s
fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:478s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:493s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:433s
fi-skl-x1585l total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:486s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:550s
fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:406s
dbfb2f62576e1c3550d10398b097589959356db3 drm-tip: 2017y-08m-21d-08h-13m-34s UTC integration manifest
8a2dfbabcac6 drm/i915/cnl: extract cnl_set_procmon_ref_values
42807a64d1c1 drm/i915/cnl: simplify cnl_procmon_values handling
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5456/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/i915/cnl: simplify cnl_procmon_values handling
2017-08-22 0:03 [PATCH 1/2] drm/i915/cnl: simplify cnl_procmon_values handling Rodrigo Vivi
2017-08-22 0:03 ` [PATCH 2/2] drm/i915/cnl: extract cnl_set_procmon_ref_values Rodrigo Vivi
2017-08-22 0:46 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: simplify cnl_procmon_values handling Patchwork
@ 2017-08-22 14:44 ` Ville Syrjälä
2017-08-22 16:24 ` Rodrigo Vivi
2 siblings, 1 reply; 5+ messages in thread
From: Ville Syrjälä @ 2017-08-22 14:44 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Paulo Zanoni
On Mon, Aug 21, 2017 at 05:03:55PM -0700, Rodrigo Vivi wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Make it a little less magical and a little simpler and more hardcoded
> so we don't end up with an array that's composed mostly of empty
> entries.
>
> v2: Add an enum for the voltage+register values (Ville).
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
For the series
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 58 +++++++++++++++++++++------------
> 1 file changed, 37 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index b66d8e136aa3..b7f4fbe7ae0d 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2707,24 +2707,27 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
> usleep_range(10, 30); /* 10 us delay per Bspec */
> }
>
> -#define CNL_PROCMON_IDX(val) \
> - (((val) & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) >> VOLTAGE_INFO_SHIFT)
> -#define NUM_CNL_PROCMON \
> - (CNL_PROCMON_IDX(VOLTAGE_INFO_MASK | PROCESS_INFO_MASK) + 1)
> +enum {
> + PROCMON_0_85V_DOT_0,
> + PROCMON_0_95V_DOT_0,
> + PROCMON_0_95V_DOT_1,
> + PROCMON_1_05V_DOT_0,
> + PROCMON_1_05V_DOT_1,
> +};
>
> static const struct cnl_procmon {
> u32 dw1, dw9, dw10;
> -} cnl_procmon_values[NUM_CNL_PROCMON] = {
> - [CNL_PROCMON_IDX(VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0)] =
> - { .dw1 = 0x00 << 16, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
> - [CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0)] =
> - { .dw1 = 0x00 << 16, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
> - [CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1)] =
> - { .dw1 = 0x00 << 16, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
> - [CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0)] =
> - { .dw1 = 0x00 << 16, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
> - [CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1)] =
> - { .dw1 = 0x44 << 16, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
> +} cnl_procmon_values[] = {
> + [PROCMON_0_85V_DOT_0] =
> + { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
> + [PROCMON_0_95V_DOT_0] =
> + { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
> + [PROCMON_0_95V_DOT_1] =
> + { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
> + [PROCMON_1_05V_DOT_0] =
> + { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
> + [PROCMON_1_05V_DOT_1] =
> + { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
> };
>
> static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
> @@ -2747,9 +2750,25 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> I915_WRITE(CHICKEN_MISC_2, val);
>
> val = I915_READ(CNL_PORT_COMP_DW3);
> - procmon = &cnl_procmon_values[CNL_PROCMON_IDX(val)];
> -
> - WARN_ON(procmon->dw10 == 0);
> + switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
> + default:
> + MISSING_CASE(val);
> + case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
> + procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
> + break;
> + case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
> + procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
> + break;
> + case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
> + procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
> + break;
> + case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
> + procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
> + break;
> + case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
> + procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
> + break;
> + }
>
> val = I915_READ(CNL_PORT_COMP_DW1);
> val &= ~((0xff << 16) | 0xff);
> @@ -2784,9 +2803,6 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> gen9_dbuf_enable(dev_priv);
> }
>
> -#undef CNL_PROCMON_IDX
> -#undef NUM_CNL_PROCMON
> -
> static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> --
> 2.13.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH 1/2] drm/i915/cnl: simplify cnl_procmon_values handling
2017-08-22 14:44 ` [PATCH 1/2] " Ville Syrjälä
@ 2017-08-22 16:24 ` Rodrigo Vivi
0 siblings, 0 replies; 5+ messages in thread
From: Rodrigo Vivi @ 2017-08-22 16:24 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Paulo Zanoni, Rodrigo Vivi
merged to dinq. thanks for the patches and review
On Tue, Aug 22, 2017 at 7:44 AM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Mon, Aug 21, 2017 at 05:03:55PM -0700, Rodrigo Vivi wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> Make it a little less magical and a little simpler and more hardcoded
>> so we don't end up with an array that's composed mostly of empty
>> entries.
>>
>> v2: Add an enum for the voltage+register values (Ville).
>>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> For the series
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>> ---
>> drivers/gpu/drm/i915/intel_runtime_pm.c | 58 +++++++++++++++++++++------------
>> 1 file changed, 37 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> index b66d8e136aa3..b7f4fbe7ae0d 100644
>> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> @@ -2707,24 +2707,27 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
>> usleep_range(10, 30); /* 10 us delay per Bspec */
>> }
>>
>> -#define CNL_PROCMON_IDX(val) \
>> - (((val) & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) >> VOLTAGE_INFO_SHIFT)
>> -#define NUM_CNL_PROCMON \
>> - (CNL_PROCMON_IDX(VOLTAGE_INFO_MASK | PROCESS_INFO_MASK) + 1)
>> +enum {
>> + PROCMON_0_85V_DOT_0,
>> + PROCMON_0_95V_DOT_0,
>> + PROCMON_0_95V_DOT_1,
>> + PROCMON_1_05V_DOT_0,
>> + PROCMON_1_05V_DOT_1,
>> +};
>>
>> static const struct cnl_procmon {
>> u32 dw1, dw9, dw10;
>> -} cnl_procmon_values[NUM_CNL_PROCMON] = {
>> - [CNL_PROCMON_IDX(VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0)] =
>> - { .dw1 = 0x00 << 16, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
>> - [CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0)] =
>> - { .dw1 = 0x00 << 16, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
>> - [CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1)] =
>> - { .dw1 = 0x00 << 16, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
>> - [CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0)] =
>> - { .dw1 = 0x00 << 16, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
>> - [CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1)] =
>> - { .dw1 = 0x44 << 16, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
>> +} cnl_procmon_values[] = {
>> + [PROCMON_0_85V_DOT_0] =
>> + { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
>> + [PROCMON_0_95V_DOT_0] =
>> + { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
>> + [PROCMON_0_95V_DOT_1] =
>> + { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
>> + [PROCMON_1_05V_DOT_0] =
>> + { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
>> + [PROCMON_1_05V_DOT_1] =
>> + { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
>> };
>>
>> static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
>> @@ -2747,9 +2750,25 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
>> I915_WRITE(CHICKEN_MISC_2, val);
>>
>> val = I915_READ(CNL_PORT_COMP_DW3);
>> - procmon = &cnl_procmon_values[CNL_PROCMON_IDX(val)];
>> -
>> - WARN_ON(procmon->dw10 == 0);
>> + switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
>> + default:
>> + MISSING_CASE(val);
>> + case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
>> + procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
>> + break;
>> + case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
>> + procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
>> + break;
>> + case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
>> + procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
>> + break;
>> + case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
>> + procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
>> + break;
>> + case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
>> + procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
>> + break;
>> + }
>>
>> val = I915_READ(CNL_PORT_COMP_DW1);
>> val &= ~((0xff << 16) | 0xff);
>> @@ -2784,9 +2803,6 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
>> gen9_dbuf_enable(dev_priv);
>> }
>>
>> -#undef CNL_PROCMON_IDX
>> -#undef NUM_CNL_PROCMON
>> -
>> static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
>> {
>> struct i915_power_domains *power_domains = &dev_priv->power_domains;
>> --
>> 2.13.2
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-08-22 16:24 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-08-22 0:03 [PATCH 1/2] drm/i915/cnl: simplify cnl_procmon_values handling Rodrigo Vivi
2017-08-22 0:03 ` [PATCH 2/2] drm/i915/cnl: extract cnl_set_procmon_ref_values Rodrigo Vivi
2017-08-22 0:46 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: simplify cnl_procmon_values handling Patchwork
2017-08-22 14:44 ` [PATCH 1/2] " Ville Syrjälä
2017-08-22 16:24 ` Rodrigo Vivi
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