From: Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
To: Zhen Lei <thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Cc: Hanjun Guo <guohanjun-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>,
Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>,
linux-kernel
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
Xinwei Hu <huxinwei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>,
iommu
<iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>,
Zefan Li <lizefan-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>,
Tianhong Ding
<dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>,
linux-arm-kernel
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
Subject: Re: [PATCH 1/5] iommu/arm-smmu-v3: put off the execution of TLBI* to reduce lock confliction
Date: Tue, 22 Aug 2017 17:41:42 +0200 [thread overview]
Message-ID: <20170822154142.GA19533@8bytes.org> (raw)
In-Reply-To: <1498484330-10840-2-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
On Mon, Jun 26, 2017 at 09:38:46PM +0800, Zhen Lei wrote:
> -static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent)
> +static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent, int optimize)
> {
> if (queue_full(q))
> return -ENOSPC;
>
> queue_write(Q_ENT(q, q->prod), ent, q->ent_dwords);
> - queue_inc_prod(q);
> +
> + /*
> + * We don't want too many commands to be delayed, this may lead the
> + * followed sync command to wait for a long time.
> + */
> + if (optimize && (++q->nr_delay < CMDQ_MAX_DELAYED)) {
> + queue_inc_swprod(q);
> + } else {
> + queue_inc_prod(q);
> + q->nr_delay = 0;
> + }
> +
> return 0;
> }
>
> @@ -909,6 +928,7 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu)
> static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
> struct arm_smmu_cmdq_ent *ent)
> {
> + int optimize = 0;
> u64 cmd[CMDQ_ENT_DWORDS];
> unsigned long flags;
> bool wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV);
> @@ -920,8 +940,17 @@ static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
> return;
> }
>
> + /*
> + * All TLBI commands should be followed by a sync command later.
> + * The CFGI commands is the same, but they are rarely executed.
> + * So just optimize TLBI commands now, to reduce the "if" judgement.
> + */
> + if ((ent->opcode >= CMDQ_OP_TLBI_NH_ALL) &&
> + (ent->opcode <= CMDQ_OP_TLBI_NSNH_ALL))
> + optimize = 1;
> +
> spin_lock_irqsave(&smmu->cmdq.lock, flags);
> - while (queue_insert_raw(q, cmd) == -ENOSPC) {
> + while (queue_insert_raw(q, cmd, optimize) == -ENOSPC) {
> if (queue_poll_cons(q, false, wfe))
> dev_err_ratelimited(smmu->dev, "CMDQ timeout\n");
> }
This doesn't look correct. How do you make sure that a given IOVA range
is flushed before the addresses are reused?
Regards,
Joerg
WARNING: multiple messages have this Message-ID (diff)
From: joro@8bytes.org (Joerg Roedel)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/5] iommu/arm-smmu-v3: put off the execution of TLBI* to reduce lock confliction
Date: Tue, 22 Aug 2017 17:41:42 +0200 [thread overview]
Message-ID: <20170822154142.GA19533@8bytes.org> (raw)
In-Reply-To: <1498484330-10840-2-git-send-email-thunder.leizhen@huawei.com>
On Mon, Jun 26, 2017 at 09:38:46PM +0800, Zhen Lei wrote:
> -static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent)
> +static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent, int optimize)
> {
> if (queue_full(q))
> return -ENOSPC;
>
> queue_write(Q_ENT(q, q->prod), ent, q->ent_dwords);
> - queue_inc_prod(q);
> +
> + /*
> + * We don't want too many commands to be delayed, this may lead the
> + * followed sync command to wait for a long time.
> + */
> + if (optimize && (++q->nr_delay < CMDQ_MAX_DELAYED)) {
> + queue_inc_swprod(q);
> + } else {
> + queue_inc_prod(q);
> + q->nr_delay = 0;
> + }
> +
> return 0;
> }
>
> @@ -909,6 +928,7 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu)
> static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
> struct arm_smmu_cmdq_ent *ent)
> {
> + int optimize = 0;
> u64 cmd[CMDQ_ENT_DWORDS];
> unsigned long flags;
> bool wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV);
> @@ -920,8 +940,17 @@ static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
> return;
> }
>
> + /*
> + * All TLBI commands should be followed by a sync command later.
> + * The CFGI commands is the same, but they are rarely executed.
> + * So just optimize TLBI commands now, to reduce the "if" judgement.
> + */
> + if ((ent->opcode >= CMDQ_OP_TLBI_NH_ALL) &&
> + (ent->opcode <= CMDQ_OP_TLBI_NSNH_ALL))
> + optimize = 1;
> +
> spin_lock_irqsave(&smmu->cmdq.lock, flags);
> - while (queue_insert_raw(q, cmd) == -ENOSPC) {
> + while (queue_insert_raw(q, cmd, optimize) == -ENOSPC) {
> if (queue_poll_cons(q, false, wfe))
> dev_err_ratelimited(smmu->dev, "CMDQ timeout\n");
> }
This doesn't look correct. How do you make sure that a given IOVA range
is flushed before the addresses are reused?
Regards,
Joerg
WARNING: multiple messages have this Message-ID (diff)
From: Joerg Roedel <joro@8bytes.org>
To: Zhen Lei <thunder.leizhen@huawei.com>
Cc: Will Deacon <will.deacon@arm.com>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
iommu <iommu@lists.linux-foundation.org>,
Robin Murphy <robin.murphy@arm.com>,
linux-kernel <linux-kernel@vger.kernel.org>,
Zefan Li <lizefan@huawei.com>, Xinwei Hu <huxinwei@huawei.com>,
Tianhong Ding <dingtianhong@huawei.com>,
Hanjun Guo <guohanjun@huawei.com>,
John Garry <john.garry@huawei.com>
Subject: Re: [PATCH 1/5] iommu/arm-smmu-v3: put off the execution of TLBI* to reduce lock confliction
Date: Tue, 22 Aug 2017 17:41:42 +0200 [thread overview]
Message-ID: <20170822154142.GA19533@8bytes.org> (raw)
In-Reply-To: <1498484330-10840-2-git-send-email-thunder.leizhen@huawei.com>
On Mon, Jun 26, 2017 at 09:38:46PM +0800, Zhen Lei wrote:
> -static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent)
> +static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent, int optimize)
> {
> if (queue_full(q))
> return -ENOSPC;
>
> queue_write(Q_ENT(q, q->prod), ent, q->ent_dwords);
> - queue_inc_prod(q);
> +
> + /*
> + * We don't want too many commands to be delayed, this may lead the
> + * followed sync command to wait for a long time.
> + */
> + if (optimize && (++q->nr_delay < CMDQ_MAX_DELAYED)) {
> + queue_inc_swprod(q);
> + } else {
> + queue_inc_prod(q);
> + q->nr_delay = 0;
> + }
> +
> return 0;
> }
>
> @@ -909,6 +928,7 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu)
> static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
> struct arm_smmu_cmdq_ent *ent)
> {
> + int optimize = 0;
> u64 cmd[CMDQ_ENT_DWORDS];
> unsigned long flags;
> bool wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV);
> @@ -920,8 +940,17 @@ static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
> return;
> }
>
> + /*
> + * All TLBI commands should be followed by a sync command later.
> + * The CFGI commands is the same, but they are rarely executed.
> + * So just optimize TLBI commands now, to reduce the "if" judgement.
> + */
> + if ((ent->opcode >= CMDQ_OP_TLBI_NH_ALL) &&
> + (ent->opcode <= CMDQ_OP_TLBI_NSNH_ALL))
> + optimize = 1;
> +
> spin_lock_irqsave(&smmu->cmdq.lock, flags);
> - while (queue_insert_raw(q, cmd) == -ENOSPC) {
> + while (queue_insert_raw(q, cmd, optimize) == -ENOSPC) {
> if (queue_poll_cons(q, false, wfe))
> dev_err_ratelimited(smmu->dev, "CMDQ timeout\n");
> }
This doesn't look correct. How do you make sure that a given IOVA range
is flushed before the addresses are reused?
Regards,
Joerg
next prev parent reply other threads:[~2017-08-22 15:41 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-26 13:38 [PATCH 0/5] arm-smmu: performance optimization Zhen Lei
2017-06-26 13:38 ` Zhen Lei
2017-06-26 13:38 ` Zhen Lei
2017-06-26 13:38 ` [PATCH 1/5] iommu/arm-smmu-v3: put off the execution of TLBI* to reduce lock confliction Zhen Lei
2017-06-26 13:38 ` Zhen Lei
[not found] ` <1498484330-10840-2-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2017-06-28 9:32 ` Will Deacon
2017-06-28 9:32 ` Will Deacon
2017-06-28 9:32 ` Will Deacon
2017-06-29 2:08 ` Leizhen (ThunderTown)
2017-06-29 2:08 ` Leizhen (ThunderTown)
2017-06-29 2:08 ` Leizhen (ThunderTown)
[not found] ` <5954610F.9020807-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2017-07-17 13:06 ` John Garry
2017-07-17 13:06 ` John Garry
2017-07-17 13:06 ` John Garry
2017-07-17 14:23 ` Jonathan Cameron
2017-07-17 14:23 ` Jonathan Cameron
2017-07-17 14:23 ` Jonathan Cameron
[not found] ` <20170717222337.0000508f-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2017-07-17 17:28 ` Nate Watterson
2017-07-17 17:28 ` Nate Watterson
2017-07-17 17:28 ` Nate Watterson
[not found] ` <3cec10c5-82ca-2c54-dfdb-ac73b16e5bc6-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-18 9:20 ` Jonathan Cameron
2017-07-18 9:20 ` Jonathan Cameron
2017-07-18 9:20 ` Jonathan Cameron
[not found] ` <20170718172055.00006e84-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2017-07-20 19:07 ` Nate Watterson
2017-07-20 19:07 ` Nate Watterson
2017-07-20 19:07 ` Nate Watterson
[not found] ` <c1d85f28-c57b-4414-3504-16afb3a19ce0-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-21 10:57 ` Jonathan Cameron
2017-07-21 10:57 ` Jonathan Cameron
2017-07-21 10:57 ` Jonathan Cameron
2017-08-22 15:41 ` Joerg Roedel [this message]
2017-08-22 15:41 ` Joerg Roedel
2017-08-22 15:41 ` Joerg Roedel
2017-08-23 1:21 ` Leizhen (ThunderTown)
2017-08-23 1:21 ` Leizhen (ThunderTown)
2017-08-23 1:21 ` Leizhen (ThunderTown)
2017-06-26 13:38 ` [PATCH 2/5] iommu: add a new member unmap_tlb_sync into struct iommu_ops Zhen Lei
2017-06-26 13:38 ` Zhen Lei
[not found] ` <1498484330-10840-1-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2017-06-26 13:38 ` [PATCH 3/5] iommu/arm-smmu-v3: add support for unmap an iova range with only one tlb sync Zhen Lei
2017-06-26 13:38 ` Zhen Lei
2017-06-26 13:38 ` Zhen Lei
2017-06-26 13:38 ` [PATCH 4/5] iommu/arm-smmu: add support for unmap a memory " Zhen Lei
2017-06-26 13:38 ` Zhen Lei
2017-06-26 13:38 ` Zhen Lei
2017-06-26 13:38 ` [PATCH 5/5] iommu/io-pgtable: delete member tlb_sync_pending of struct io_pgtable Zhen Lei
2017-06-26 13:38 ` Zhen Lei
2017-06-26 13:38 ` Zhen Lei
2017-08-17 14:36 ` [PATCH 0/5] arm-smmu: performance optimization Will Deacon
2017-08-17 14:36 ` Will Deacon
2017-08-17 14:36 ` Will Deacon
[not found] ` <20170817143650.GB30338-5wv7dgnIgG8@public.gmane.org>
2017-08-18 3:19 ` Leizhen (ThunderTown)
2017-08-18 3:19 ` Leizhen (ThunderTown)
2017-08-18 3:19 ` Leizhen (ThunderTown)
2017-08-18 8:39 ` Will Deacon
2017-08-18 8:39 ` Will Deacon
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