Re: [PATCH] MIPS: Add basic R5900 support

[Fredrik Noring <noring@nocrew.org>]

Hi Maciej,

Thank you for your review!

>  Is there an external explicitly-driven write-back buffer there with the 
> R5900?  That would be odd with a MIPS III ISA processor, however if there 
> indeed is, then I think the CPU_HAS_WB setting needs to go along with the 
> code that implements `__wbflush' for this platform.

The C790 block diagram contains a WBB connected to the BIU bus (p. 2-2) in the
"TX System RISC TX79 Core Architecture" manual:

    The Writeback Buffer (WBB) is an 8 entry by 16 byte (one quadword) FIFO
    queuing up stores prior to accessing the CPU bus. It increases C790
    performance by decoupling the processor from the latencies of the CPU bus.
    It is also used during the gathering operation of uncached accelerated
    stores; sequential stores less than a quadword in length are gathered in
    the WBB, thereby reducing bus bandwidth usage. (p. 2-4)

__wbflush is implemented in arch/mips/ps2/setup.c:193 in the remaining patch
(link below):

static void ps2_wbflush(void)
{
	__asm__ __volatile__("sync.l":::"memory");

	/* flush write buffer to bus */
	inl(ps2sif_bustophys(0));
}

https://github.com/frno7/linux/blob/ps2-v4.12-squashed/arch/mips/ps2/setup.c#L193

Then ps2sif_bustophys is implemented in arch/mips/ps2/iopheap.c:

phys_addr_t ps2sif_bustophys(dma_addr_t a)
{
	return(a + PS2_IOP_HEAP_BASE);
}

which in turn uses

#define PS2_IOP_HEAP_BASE 0x1c000000

from arch/mips/include/asm/mach-ps2/ps2.h. Would you like to move this code
somewhere else to go along with the declaration of CPU_HAS_WB?

>  Shouldn't it go along with `R4000 class processors' earlier above?

Sure!

>  If this is a MIPS III base ISA implementation, then presumably you need 
> to set `c->fpu_msk31' as well, to exclude FPU_CSR_CONDX bits introduced 
> with the MIPS IV ISA only.  Double-check with hardware documentation for 
> the details.

Good catch, I'm checking it with the "TX System RISC TX79 Core Architecture"
manual (link below). The FPU is IEEE754-1985 compatible MIPS III ISA (p. 1-2),
the same as the TX49HF CPU core (p. 2-18). FCR31 looks like this (p. 10-6):

    31       25 24 23 22  18 17   12 11      7 6     2 1  0
    +----------+--+--+------+-------+---------+-------+----+
    |    0     |FS| C|   0  | Cause | Enables | Flags | RM |
    +----------+--+--+------+-------+---------+-------+----+
         7       1  1    5      6        5        5      2

http://www.lukasz.dk/files/tx79architecture.pdf

Fredrik