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From: jan.glauber@caviumnetworks.com (Jan Glauber)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU counters
Date: Thu, 31 Aug 2017 17:27:23 +0200	[thread overview]
Message-ID: <20170831152723.GA23982@hc> (raw)
In-Reply-To: <c6d79504-dfa8-a3fe-bd2b-20ac867e2514@arm.com>

On Thu, Aug 31, 2017 at 02:26:22PM +0100, Suzuki K Poulose wrote:
> On 31/08/17 12:35, Jan Glauber wrote:
> >On Wed, Aug 30, 2017 at 11:03:00AM +0100, Suzuki K Poulose wrote:
> >>On 29/08/17 14:12, Jan Glauber wrote:

[...]

> >>>+/* LMC events */
> >>>+#define LMC_EVENT_IFB_CNT		0x1d0
> >>>+#define LMC_EVENT_OPS_CNT		0x1d8
> >>>+#define LMC_EVENT_DCLK_CNT		0x1e0
> >>>+#define LMC_EVENT_BANK_CONFLICT1	0x360
> >>>+#define LMC_EVENT_BANK_CONFLICT2	0x368
> >>>+
> >>>+#define CVM_PMU_LMC_EVENT_ATTR(_name, _id)						\
> >>>+	&((struct perf_pmu_events_attr[]) {						\
> >>>+		{									\
> >>>+			__ATTR(_name, S_IRUGO, cvm_pmu_event_sysfs_show, NULL),		\
> >>>+			_id,								\
> >>>+			"lmc_event=" __stringify(_id),					\
> >>>+		}									\
> >>>+	})[0].attr.attr
> >>>+
> >>>+/* map counter numbers to register offsets */
> >>>+static int lmc_events[] = {
> >>>+	LMC_EVENT_IFB_CNT,
> >>>+	LMC_EVENT_OPS_CNT,
> >>>+	LMC_EVENT_DCLK_CNT,
> >>>+	LMC_EVENT_BANK_CONFLICT1,
> >>>+	LMC_EVENT_BANK_CONFLICT2,
> >>>+};
> >>>+
> >>>+static int cvm_pmu_lmc_add(struct perf_event *event, int flags)
> >>>+{
> >>>+	struct hw_perf_event *hwc = &event->hw;
> >>>+
> >>>+	return cvm_pmu_add(event, flags, LMC_CONFIG_OFFSET,
> >>>+			   lmc_events[hwc->config]);
> >>>+}
> >>>+
> >>
> >>Is there any reason why we can't use the LMC event code directly
> >>here, avoiding the mapping altogether ?
> >
> >I wanted to avoid exposing the raw numbers (0x1d0 - 0x368) here.
> 
> Thats the primarily the reason why we expose the "aliases" in events/.
> The other problem with adding another layer of mapping is, you are preventing
> someone from actually mapping the raw code used by the perf tool (which is now
> a mapping index) to the real raw code used by the hardware unless they have
> the kernel source handy. If you choose to expose the raw numbers, like *all*
> the other PMUs, the user can map it by looking up the manual.

So what would that do to the config bits? Currently they are:
PMU_FORMAT_ATTR(lmc_event, "config:0-2");

Should I have config:0-9 then? Wouldn't that be confusing as there are
only 5 events?

Also I need to be very careful as we need to prevent a user from
accessing anything else then the counters. I can do that with the
event_valid callback though.

thanks,
Jan

> Cheers
> Suzuki

WARNING: multiple messages have this Message-ID (diff)
From: Jan Glauber <jan.glauber@caviumnetworks.com>
To: Suzuki K Poulose <Suzuki.Poulose@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Will Deacon <will.deacon@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Borislav Petkov <bp@alien8.de>,
	David Daney <david.daney@cavium.com>
Subject: Re: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU counters
Date: Thu, 31 Aug 2017 17:27:23 +0200	[thread overview]
Message-ID: <20170831152723.GA23982@hc> (raw)
In-Reply-To: <c6d79504-dfa8-a3fe-bd2b-20ac867e2514@arm.com>

On Thu, Aug 31, 2017 at 02:26:22PM +0100, Suzuki K Poulose wrote:
> On 31/08/17 12:35, Jan Glauber wrote:
> >On Wed, Aug 30, 2017 at 11:03:00AM +0100, Suzuki K Poulose wrote:
> >>On 29/08/17 14:12, Jan Glauber wrote:

[...]

> >>>+/* LMC events */
> >>>+#define LMC_EVENT_IFB_CNT		0x1d0
> >>>+#define LMC_EVENT_OPS_CNT		0x1d8
> >>>+#define LMC_EVENT_DCLK_CNT		0x1e0
> >>>+#define LMC_EVENT_BANK_CONFLICT1	0x360
> >>>+#define LMC_EVENT_BANK_CONFLICT2	0x368
> >>>+
> >>>+#define CVM_PMU_LMC_EVENT_ATTR(_name, _id)						\
> >>>+	&((struct perf_pmu_events_attr[]) {						\
> >>>+		{									\
> >>>+			__ATTR(_name, S_IRUGO, cvm_pmu_event_sysfs_show, NULL),		\
> >>>+			_id,								\
> >>>+			"lmc_event=" __stringify(_id),					\
> >>>+		}									\
> >>>+	})[0].attr.attr
> >>>+
> >>>+/* map counter numbers to register offsets */
> >>>+static int lmc_events[] = {
> >>>+	LMC_EVENT_IFB_CNT,
> >>>+	LMC_EVENT_OPS_CNT,
> >>>+	LMC_EVENT_DCLK_CNT,
> >>>+	LMC_EVENT_BANK_CONFLICT1,
> >>>+	LMC_EVENT_BANK_CONFLICT2,
> >>>+};
> >>>+
> >>>+static int cvm_pmu_lmc_add(struct perf_event *event, int flags)
> >>>+{
> >>>+	struct hw_perf_event *hwc = &event->hw;
> >>>+
> >>>+	return cvm_pmu_add(event, flags, LMC_CONFIG_OFFSET,
> >>>+			   lmc_events[hwc->config]);
> >>>+}
> >>>+
> >>
> >>Is there any reason why we can't use the LMC event code directly
> >>here, avoiding the mapping altogether ?
> >
> >I wanted to avoid exposing the raw numbers (0x1d0 - 0x368) here.
> 
> Thats the primarily the reason why we expose the "aliases" in events/.
> The other problem with adding another layer of mapping is, you are preventing
> someone from actually mapping the raw code used by the perf tool (which is now
> a mapping index) to the real raw code used by the hardware unless they have
> the kernel source handy. If you choose to expose the raw numbers, like *all*
> the other PMUs, the user can map it by looking up the manual.

So what would that do to the config bits? Currently they are:
PMU_FORMAT_ATTR(lmc_event, "config:0-2");

Should I have config:0-9 then? Wouldn't that be confusing as there are
only 5 events?

Also I need to be very careful as we need to prevent a user from
accessing anything else then the counters. I can do that with the
event_valid callback though.

thanks,
Jan

> Cheers
> Suzuki

  reply	other threads:[~2017-08-31 15:27 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-29 13:12 [RFC PATCH v9 0/7] Cavium ARM64 uncore PMU support Jan Glauber
2017-08-29 13:12 ` Jan Glauber
2017-08-29 13:12 ` [RFC PATCH v9 1/7] edac: thunderx: Remove suspend/resume support Jan Glauber
2017-08-29 13:12   ` Jan Glauber
2017-08-30 17:54   ` Borislav Petkov
2017-08-30 17:54     ` Borislav Petkov
2017-08-31  8:46     ` Jan Glauber
2017-08-31  8:46       ` Jan Glauber
2017-08-29 13:12 ` [RFC PATCH v9 2/7] edac, soc: thunderx: Add wrapper for EDAC LMC PCI device Jan Glauber
2017-08-29 13:12   ` [RFC PATCH v9 2/7] edac,soc: " Jan Glauber
2017-08-29 13:12 ` [RFC PATCH v9 3/7] edac, soc: thunderx: Add wrapper for EDAC OCX " Jan Glauber
2017-08-29 13:12   ` [RFC PATCH v9 3/7] edac,soc: " Jan Glauber
2017-08-29 13:12 ` [RFC PATCH v9 4/7] perf: export perf_event_update_userpage() Jan Glauber
2017-08-29 13:12   ` Jan Glauber
2017-08-29 13:12 ` [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU counters Jan Glauber
2017-08-29 13:12   ` Jan Glauber
2017-08-30  2:54   ` Zhangshaokun
2017-08-30  2:54     ` Zhangshaokun
2017-08-31  9:57     ` Jan Glauber
2017-08-31  9:57       ` Jan Glauber
2017-08-31 10:31       ` Mark Rutland
2017-08-31 10:31         ` Mark Rutland
2017-08-31 11:13         ` Jan Glauber
2017-08-31 11:13           ` Jan Glauber
2017-08-31 11:18         ` Jan Glauber
2017-08-31 11:18           ` Jan Glauber
2017-08-30 10:03   ` Suzuki K Poulose
2017-08-30 10:03     ` Suzuki K Poulose
2017-08-31 11:35     ` Jan Glauber
2017-08-31 11:35       ` Jan Glauber
2017-08-31 13:26       ` Suzuki K Poulose
2017-08-31 13:26         ` Suzuki K Poulose
2017-08-31 15:27         ` Jan Glauber [this message]
2017-08-31 15:27           ` Jan Glauber
2017-08-29 13:12 ` [RFC PATCH v9 6/7] perf: cavium: Support transmit-link " Jan Glauber
2017-08-29 13:12   ` Jan Glauber
2017-08-29 13:12 ` [RFC PATCH v9 7/7] perf: cavium: Add Documentation Jan Glauber
2017-08-29 13:12   ` Jan Glauber
2017-08-31 11:38 ` [RFC PATCH v9 0/7] Cavium ARM64 uncore PMU support Jan Glauber
2017-08-31 11:38   ` Jan Glauber

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