From: Stephen Boyd <sboyd@codeaurora.org>
To: Quentin Schulz <quentin.schulz@free-electrons.com>
Cc: mark.rutland@arm.com, boris.brezillon@free-electrons.com,
alsa-devel@alsa-project.org, thomas.petazzoni@free-electrons.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
mturquette@baylibre.com, tiwai@suse.com,
Nicolas Ferre <nicolas.ferre@atmel.com>,
lgirdwood@gmail.com, robh+dt@kernel.org,
alexandre.belloni@free-electrons.com, broonie@kernel.org,
cyrille.pitchen@wedev4u.fr, linux@armlinux.org.uk,
perex@perex.cz, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5 3/7] clk: at91: add audio pll clock drivers
Date: Fri, 1 Sep 2017 15:55:14 -0700 [thread overview]
Message-ID: <20170901225514.GE21656@codeaurora.org> (raw)
In-Reply-To: <f1c7acbfec384c2c33bf340464a98b731dac8c0c.1502346448.git-series.quentin.schulz@free-electrons.com>
On 08/10, Quentin Schulz wrote:
> This new clock driver set allows to have a fractional divided clock that
> would generate a precise clock particularly suitable for audio
> applications.
>
> The main audio pll clock has two children clocks: one that is connected
> to the PMC, the other that can directly drive a pad. As these two routes
> have different enable bits and different dividers and divider formulas,
> they are handled by two different drivers. Each of them could modify the
> rate of the main audio pll parent.
>
> The main audio pll clock can output 620MHz to 700MHz.
>
> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@codeaurora.org>
To: Quentin Schulz <quentin.schulz@free-electrons.com>
Cc: mturquette@baylibre.com, robh+dt@kernel.org,
mark.rutland@arm.com, lgirdwood@gmail.com, broonie@kernel.org,
nicolas.ferre@microchip.com,
alexandre.belloni@free-electrons.com, linux@armlinux.org.uk,
boris.brezillon@free-electrons.com, perex@perex.cz,
tiwai@suse.com, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
alsa-devel@alsa-project.org,
linux-arm-kernel@lists.infradead.org, cyrille.pitchen@wedev4u.fr,
thomas.petazzoni@free-electrons.com,
Nicolas Ferre <nicolas.ferre@atmel.com>
Subject: Re: [PATCH v5 3/7] clk: at91: add audio pll clock drivers
Date: Fri, 1 Sep 2017 15:55:14 -0700 [thread overview]
Message-ID: <20170901225514.GE21656@codeaurora.org> (raw)
In-Reply-To: <f1c7acbfec384c2c33bf340464a98b731dac8c0c.1502346448.git-series.quentin.schulz@free-electrons.com>
On 08/10, Quentin Schulz wrote:
> This new clock driver set allows to have a fractional divided clock that
> would generate a precise clock particularly suitable for audio
> applications.
>
> The main audio pll clock has two children clocks: one that is connected
> to the PMC, the other that can directly drive a pad. As these two routes
> have different enable bits and different dividers and divider formulas,
> they are handled by two different drivers. Each of them could modify the
> rate of the main audio pll parent.
>
> The main audio pll clock can output 620MHz to 700MHz.
>
> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 3/7] clk: at91: add audio pll clock drivers
Date: Fri, 1 Sep 2017 15:55:14 -0700 [thread overview]
Message-ID: <20170901225514.GE21656@codeaurora.org> (raw)
In-Reply-To: <f1c7acbfec384c2c33bf340464a98b731dac8c0c.1502346448.git-series.quentin.schulz@free-electrons.com>
On 08/10, Quentin Schulz wrote:
> This new clock driver set allows to have a fractional divided clock that
> would generate a precise clock particularly suitable for audio
> applications.
>
> The main audio pll clock has two children clocks: one that is connected
> to the PMC, the other that can directly drive a pad. As these two routes
> have different enable bits and different dividers and divider formulas,
> they are handled by two different drivers. Each of them could modify the
> rate of the main audio pll parent.
>
> The main audio pll clock can output 620MHz to 700MHz.
>
> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2017-09-01 22:55 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-10 6:34 [PATCH v5 0/7] add support for Sama5d2 audio PLLs and enable ClassD Quentin Schulz
2017-08-10 6:34 ` Quentin Schulz
2017-08-10 6:34 ` Quentin Schulz
2017-08-10 6:34 ` [PATCH v5 1/7] clk: at91: clk-generated: remove useless divisor loop Quentin Schulz
2017-08-10 6:34 ` Quentin Schulz
[not found] ` <fe26a470c87e39b5e07fbada6ce7020a6b65429b.1502346448.git-series.quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-09-01 22:55 ` Stephen Boyd
2017-09-01 22:55 ` Stephen Boyd
2017-09-01 22:55 ` Stephen Boyd
2017-08-10 6:34 ` [PATCH v5 2/7] dt-bindings: clk: at91: add audio plls to the compatible list Quentin Schulz
2017-08-10 6:34 ` Quentin Schulz
2017-09-01 22:55 ` Stephen Boyd
2017-09-01 22:55 ` Stephen Boyd
2017-08-10 6:34 ` [PATCH v5 3/7] clk: at91: add audio pll clock drivers Quentin Schulz
2017-08-10 6:34 ` Quentin Schulz
2017-08-10 6:34 ` Quentin Schulz
2017-09-01 22:55 ` Stephen Boyd [this message]
2017-09-01 22:55 ` Stephen Boyd
2017-09-01 22:55 ` Stephen Boyd
2017-08-10 6:34 ` [PATCH v5 4/7] clk: at91: clk-generated: create function to find best_diff Quentin Schulz
2017-08-10 6:34 ` Quentin Schulz
2017-08-10 6:34 ` Quentin Schulz
2017-09-01 22:55 ` Stephen Boyd
2017-09-01 22:55 ` Stephen Boyd
2017-08-10 6:34 ` [PATCH v5 5/7] clk: at91: clk-generated: make gclk determine audio_pll rate Quentin Schulz
2017-08-10 6:34 ` Quentin Schulz
2017-08-10 6:34 ` Quentin Schulz
2017-09-01 22:55 ` Stephen Boyd
2017-09-01 22:55 ` Stephen Boyd
2017-08-10 6:34 ` [PATCH v5 6/7] ASoC: atmel-classd: remove aclk clock from DT binding Quentin Schulz
2017-08-10 6:34 ` Quentin Schulz
2017-08-10 6:34 ` Quentin Schulz
[not found] ` <baa9ebcc16cba5f41ee5b01895ec7cfce60a8ddc.1502346448.git-series.quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-09-01 22:55 ` Stephen Boyd
2017-09-01 22:55 ` Stephen Boyd
2017-09-01 22:55 ` Stephen Boyd
2017-08-10 6:34 ` [PATCH v5 7/7] ASoC: atmel-classd: remove aclk clock Quentin Schulz
2017-08-10 6:34 ` Quentin Schulz
2017-08-10 6:34 ` Quentin Schulz
2017-09-01 22:55 ` Stephen Boyd
2017-09-01 22:55 ` Stephen Boyd
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