[PATCH 1/4] drm/amd/powerplay: refine code for thermal control in powerplay

[PATCH 1/4] drm/amd/powerplay: refine code for thermal control in powerplay

[Rex Zhu]

add function point start_thermal_controller in hwmgr,
delete thermal function table and related functions

Change-Id: I61db5b7e37d75fdc55acd570369ca833b5346d01
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  |   6 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        |   1 +
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   |   4 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 148 +++------------------
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h |   5 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |   2 +-
 .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c   | 137 +++----------------
 .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h   |  13 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |   3 +-
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h         |   6 +-
 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c      |   6 +-
 11 files changed, 55 insertions(+), 276 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index ce378bd..a3991c0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -306,8 +306,10 @@ int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRa
 		range.min = temperature_range->min;
 	}
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-			PHM_PlatformCaps_ThermalController))
-		return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), &range, NULL);
+			PHM_PlatformCaps_ThermalController)
+			&& hwmgr->hwmgr_func->start_thermal_controller != NULL)
+		return hwmgr->hwmgr_func->start_thermal_controller(hwmgr, &range);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 19b6f11..f0d0d1f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -73,6 +73,7 @@ int hwmgr_early_init(struct pp_instance *handle)
 	hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 	hwmgr_init_default_caps(hwmgr);
 	hwmgr_set_user_specify_caps(hwmgr);
+	hwmgr->fan_ctrl_is_in_default_mode = true;
 
 	switch (hwmgr->chip_family) {
 	case AMDGPU_FAMILY_CZ:
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 7894978..781a05e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2284,7 +2284,6 @@ static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 {
 	kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
-	pp_smu7_thermal_fini(hwmgr);
 	kfree(hwmgr->backend);
 	hwmgr->backend = NULL;
 
@@ -2301,8 +2300,6 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 		return -ENOMEM;
 
 	hwmgr->backend = data;
-	pp_smu7_thermal_initialize(hwmgr);
-
 	smu7_patch_voltage_workaround(hwmgr);
 	smu7_init_dpm_defaults(hwmgr);
 
@@ -4660,6 +4657,7 @@ static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
 	.set_power_profile_state = smu7_set_power_profile_state,
 	.avfs_control = smu7_avfs_control,
 	.disable_smc_firmware_ctf = smu7_thermal_disable_alert,
+	.start_thermal_controller = smu7_start_thermal_controller,
 };
 
 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
index baddb56..da9e842 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
@@ -367,7 +367,7 @@ static int smu7_thermal_initialize(struct pp_hwmgr *hwmgr)
 *
 * @param    hwmgr The address of the hardware manager.
 */
-int smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr)
+static void smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr)
 {
 	uint32_t alert;
 
@@ -378,7 +378,7 @@ int smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr)
 			CG_THERMAL_INT, THERM_INT_MASK, alert);
 
 	/* send message to SMU to enable internal thermal interrupts */
-	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable);
+	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable);
 }
 
 /**
@@ -423,8 +423,7 @@ int smu7_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
 * @param    Result the last failure code
 * @return   result from set temperature range routine
 */
-static int tf_smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result)
+static int smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
 {
 /* If the fantable setup has failed we could have disabled
  * PHM_PlatformCaps_MicrocodeFanControl even after
@@ -440,108 +439,34 @@ static int tf_smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-/**
-* Set temperature range for high and low alerts
-* @param    hwmgr  the address of the powerplay hardware manager.
-* @param    pInput the pointer to input data
-* @param    pOutput the pointer to output data
-* @param    pStorage the pointer to temporary storage
-* @param    Result the last failure code
-* @return   result from set temperature range routine
-*/
-static int tf_smu7_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result)
+int smu7_start_thermal_controller(struct pp_hwmgr *hwmgr,
+				struct PP_TemperatureRange *range)
 {
-	struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
+	int ret = 0;
 
 	if (range == NULL)
 		return -EINVAL;
 
-	return smu7_thermal_set_temperature_range(hwmgr, range->min, range->max);
-}
-
-/**
-* Programs one-time setting registers
-* @param    hwmgr  the address of the powerplay hardware manager.
-* @param    pInput the pointer to input data
-* @param    pOutput the pointer to output data
-* @param    pStorage the pointer to temporary storage
-* @param    Result the last failure code
-* @return   result from initialize thermal controller routine
-*/
-static int tf_smu7_thermal_initialize(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result)
-{
-	return smu7_thermal_initialize(hwmgr);
-}
-
-/**
-* Enable high and low alerts
-* @param    hwmgr  the address of the powerplay hardware manager.
-* @param    pInput the pointer to input data
-* @param    pOutput the pointer to output data
-* @param    pStorage the pointer to temporary storage
-* @param    Result the last failure code
-* @return   result from enable alert routine
-*/
-static int tf_smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result)
-{
-	return smu7_thermal_enable_alert(hwmgr);
-}
-
-/**
-* Disable high and low alerts
-* @param    hwmgr  the address of the powerplay hardware manager.
-* @param    pInput the pointer to input data
-* @param    pOutput the pointer to output data
-* @param    pStorage the pointer to temporary storage
-* @param    Result the last failure code
-* @return   result from disable alert routine
-*/
-static int tf_smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result)
-{
-	return smu7_thermal_disable_alert(hwmgr);
-}
+	smu7_thermal_initialize(hwmgr);
+	ret = smu7_thermal_set_temperature_range(hwmgr, range->min, range->max);
+	if (ret)
+		return -EINVAL;
+	smu7_thermal_enable_alert(hwmgr);
+	ret = smum_thermal_avfs_enable(hwmgr);
+	if (ret)
+		return -EINVAL;
 
-static const struct phm_master_table_item
-phm_thermal_start_thermal_controller_master_list[] = {
-	{ .tableFunction = tf_smu7_thermal_initialize },
-	{ .tableFunction = tf_smu7_thermal_set_temperature_range },
-	{ .tableFunction = tf_smu7_thermal_enable_alert },
-	{ .tableFunction = smum_thermal_avfs_enable },
 /* We should restrict performance levels to low before we halt the SMC.
  * On the other hand we are still in boot state when we do this
  * so it would be pointless.
  * If this assumption changes we have to revisit this table.
  */
-	{ .tableFunction = smum_thermal_setup_fan_table },
-	{ .tableFunction = tf_smu7_thermal_start_smc_fan_control },
-	{ }
-};
-
-static const struct phm_master_table_header
-phm_thermal_start_thermal_controller_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	phm_thermal_start_thermal_controller_master_list
-};
-
-static const struct phm_master_table_item
-phm_thermal_set_temperature_range_master_list[] = {
-	{ .tableFunction = tf_smu7_thermal_disable_alert },
-	{ .tableFunction = tf_smu7_thermal_set_temperature_range },
-	{ .tableFunction = tf_smu7_thermal_enable_alert },
-	{ }
-};
-
-static const struct phm_master_table_header
-phm_thermal_set_temperature_range_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	phm_thermal_set_temperature_range_master_list
-};
+	smum_thermal_setup_fan_table(hwmgr);
+	smu7_thermal_start_smc_fan_control(hwmgr);
+	return 0;
+}
+
+
 
 int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
 {
@@ -549,36 +474,3 @@ int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
 		smu7_fan_ctrl_set_default_mode(hwmgr);
 	return 0;
 }
-
-/**
-* Initializes the thermal controller related functions in the Hardware Manager structure.
-* @param    hwmgr The address of the hardware manager.
-* @exception Any error code from the low-level communication.
-*/
-int pp_smu7_thermal_initialize(struct pp_hwmgr *hwmgr)
-{
-	int result;
-
-	result = phm_construct_table(hwmgr,
-			&phm_thermal_set_temperature_range_master,
-			&(hwmgr->set_temperature_range));
-
-	if (!result) {
-		result = phm_construct_table(hwmgr,
-				&phm_thermal_start_thermal_controller_master,
-				&(hwmgr->start_thermal_controller));
-		if (result)
-			phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));
-	}
-
-	if (!result)
-		hwmgr->fan_ctrl_is_in_default_mode = true;
-	return result;
-}
-
-void pp_smu7_thermal_fini(struct pp_hwmgr *hwmgr)
-{
-	phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));
-	phm_destroy_table(hwmgr, &(hwmgr->start_thermal_controller));
-	return;
-}
\ No newline at end of file
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h
index ba71b60..42c1ba0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h
@@ -46,14 +46,13 @@
 extern int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
 extern int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
 extern int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
-extern int pp_smu7_thermal_initialize(struct pp_hwmgr *hwmgr);
-extern void pp_smu7_thermal_fini(struct pp_hwmgr *hwmgr);
 extern int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
 extern int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
 extern int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
 extern int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
-extern int smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr);
 extern int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr);
 extern int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
+extern int smu7_start_thermal_controller(struct pp_hwmgr *hwmgr,
+				struct PP_TemperatureRange *temperature_range);
 #endif
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 5110086..e5f530b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -5116,6 +5116,6 @@ int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
 {
 	hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
 	hwmgr->pptable_func = &vega10_pptable_funcs;
-	pp_vega10_thermal_initialize(hwmgr);
+
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
index d8551ae..4238fd4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
@@ -554,8 +554,7 @@ int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
 * @param    Result the last failure code
 * @return   result from set temperature range routine
 */
-int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result)
+int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
 {
 	int ret;
 	struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
@@ -619,8 +618,7 @@ int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
 * @param    Result the last failure code
 * @return   result from set temperature range routine
 */
-int tf_vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result)
+int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
 {
 /* If the fantable setup has failed we could have disabled
  * PHM_PlatformCaps_MicrocodeFanControl even after
@@ -635,107 +633,37 @@ int tf_vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-/**
-* Set temperature range for high and low alerts
-* @param    hwmgr  the address of the powerplay hardware manager.
-* @param    pInput the pointer to input data
-* @param    pOutput the pointer to output data
-* @param    pStorage the pointer to temporary storage
-* @param    Result the last failure code
-* @return   result from set temperature range routine
-*/
-int tf_vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result)
+
+int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
+				struct PP_TemperatureRange *range)
 {
-	struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
+	int ret = 0;
 
 	if (range == NULL)
 		return -EINVAL;
 
-	return vega10_thermal_set_temperature_range(hwmgr, range);
-}
-
-/**
-* Programs one-time setting registers
-* @param    hwmgr  the address of the powerplay hardware manager.
-* @param    pInput the pointer to input data
-* @param    pOutput the pointer to output data
-* @param    pStorage the pointer to temporary storage
-* @param    Result the last failure code
-* @return   result from initialize thermal controller routine
-*/
-int tf_vega10_thermal_initialize(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result)
-{
-	return vega10_thermal_initialize(hwmgr);
-}
-
-/**
-* Enable high and low alerts
-* @param    hwmgr  the address of the powerplay hardware manager.
-* @param    pInput the pointer to input data
-* @param    pOutput the pointer to output data
-* @param    pStorage the pointer to temporary storage
-* @param    Result the last failure code
-* @return   result from enable alert routine
-*/
-int tf_vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result)
-{
-	return vega10_thermal_enable_alert(hwmgr);
-}
-
-/**
-* Disable high and low alerts
-* @param    hwmgr  the address of the powerplay hardware manager.
-* @param    pInput the pointer to input data
-* @param    pOutput the pointer to output data
-* @param    pStorage the pointer to temporary storage
-* @param    Result the last failure code
-* @return   result from disable alert routine
-*/
-static int tf_vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result)
-{
-	return vega10_thermal_disable_alert(hwmgr);
-}
+	vega10_thermal_initialize(hwmgr);
+	ret = vega10_thermal_set_temperature_range(hwmgr, range);
+	if (ret)
+		return -EINVAL;
 
-static struct phm_master_table_item
-vega10_thermal_start_thermal_controller_master_list[] = {
-	{ .tableFunction = tf_vega10_thermal_initialize },
-	{ .tableFunction = tf_vega10_thermal_set_temperature_range },
-	{ .tableFunction = tf_vega10_thermal_enable_alert },
+	vega10_thermal_enable_alert(hwmgr);
 /* We should restrict performance levels to low before we halt the SMC.
  * On the other hand we are still in boot state when we do this
  * so it would be pointless.
  * If this assumption changes we have to revisit this table.
  */
-	{ .tableFunction = tf_vega10_thermal_setup_fan_table },
-	{ .tableFunction = tf_vega10_thermal_start_smc_fan_control },
-	{ }
-};
+	ret = vega10_thermal_setup_fan_table(hwmgr);
+	if (ret)
+		return -EINVAL;
 
-static struct phm_master_table_header
-vega10_thermal_start_thermal_controller_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	vega10_thermal_start_thermal_controller_master_list
-};
+	vega10_thermal_start_smc_fan_control(hwmgr);
 
-static struct phm_master_table_item
-vega10_thermal_set_temperature_range_master_list[] = {
-	{ .tableFunction = tf_vega10_thermal_disable_alert },
-	{ .tableFunction = tf_vega10_thermal_set_temperature_range },
-	{ .tableFunction = tf_vega10_thermal_enable_alert },
-	{ }
+	return 0;
 };
 
-struct phm_master_table_header
-vega10_thermal_set_temperature_range_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	vega10_thermal_set_temperature_range_master_list
-};
+
+
 
 int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
 {
@@ -745,32 +673,3 @@ int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
 	}
 	return 0;
 }
-
-/**
-* Initializes the thermal controller related functions
-* in the Hardware Manager structure.
-* @param    hwmgr The address of the hardware manager.
-* @exception Any error code from the low-level communication.
-*/
-int pp_vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
-{
-	int result;
-
-	result = phm_construct_table(hwmgr,
-			&vega10_thermal_set_temperature_range_master,
-			&(hwmgr->set_temperature_range));
-
-	if (!result) {
-		result = phm_construct_table(hwmgr,
-				&vega10_thermal_start_thermal_controller_master,
-				&(hwmgr->start_thermal_controller));
-		if (result)
-			phm_destroy_table(hwmgr,
-					&(hwmgr->set_temperature_range));
-	}
-
-	if (!result)
-		hwmgr->fan_ctrl_is_in_default_mode = true;
-	return result;
-}
-
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
index 776f3a2..f34ce04 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
@@ -50,13 +50,6 @@ struct vega10_temperature {
 #define FDO_PWM_MODE_STATIC_RPM 5
 
 
-extern int tf_vega10_thermal_initialize(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result);
-extern int tf_vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result);
-extern int tf_vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result);
-
 extern int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr);
 extern int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
 extern int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
@@ -69,7 +62,6 @@ extern int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr,
 extern int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
 		uint32_t speed);
 extern int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
-extern int pp_vega10_thermal_initialize(struct pp_hwmgr *hwmgr);
 extern int vega10_thermal_ctrl_uninitialize_thermal_controller(
 		struct pp_hwmgr *hwmgr);
 extern int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr,
@@ -77,9 +69,10 @@ extern int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr,
 extern int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr,
 		uint32_t *speed);
 extern int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
-extern uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr);
 extern int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr);
-int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
+extern int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
+
+extern uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr);
 
 #endif
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 3bbe7d5..831add4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -380,6 +380,7 @@ struct pp_hwmgr_func {
 	int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
 	int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
 	int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
+	int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
 };
 
 struct pp_table_func {
@@ -766,8 +767,6 @@ struct pp_hwmgr {
 	struct phm_runtime_table_header set_power_state;
 	struct phm_runtime_table_header enable_clock_power_gatings;
 	struct phm_runtime_table_header display_configuration_changed;
-	struct phm_runtime_table_header start_thermal_controller;
-	struct phm_runtime_table_header set_temperature_range;
 	const struct pp_hwmgr_func *hwmgr_func;
 	const struct pp_table_func *pptable_func;
 	struct pp_power_state    *ps;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 5d61cc9..eb66091 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -186,10 +186,8 @@ extern int smu_allocate_memory(void *device, uint32_t size,
 
 extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
 extern int smum_process_firmware_header(struct pp_hwmgr *hwmgr);
-extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result);
-extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result);
+extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr);
+extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
 extern int smum_init_smc_table(struct pp_hwmgr *hwmgr);
 extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
 extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index f62c875..6de92cb 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -113,8 +113,7 @@ int smum_early_init(struct pp_instance *handle)
 	return 0;
 }
 
-int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result)
+int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
 {
 	if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable)
 		return hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable(hwmgr);
@@ -122,8 +121,7 @@ int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
-		void *input, void *output, void *storage, int result)
+int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
 {
 	if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table)
 		return hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table(hwmgr);
-- 
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/4] drm/amd/powerplay: refine powerplay code for CZ/ST

[Rex Zhu]

1. add function points instand of creat function tables
2. implement stop dpm tasks for CZ/ST

Change-Id: Ibe6fc92b989ba125da34857ce8b056e8b699b41b
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 .../drm/amd/powerplay/hwmgr/cz_clockpowergating.c  |  30 --
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     | 377 +++++++++------------
 2 files changed, 159 insertions(+), 248 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
index b33935f..5baf1a4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
@@ -103,16 +103,6 @@ int cz_phm_ungate_all_display_phys(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-static int cz_tf_uvd_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result)
-{
-	return 0;
-}
-
-static int cz_tf_vce_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result)
-{
-	return 0;
-}
-
 int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
 {
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
@@ -221,23 +211,3 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
 	return 0;
 }
 
-
-static const struct phm_master_table_item cz_enable_clock_power_gatings_list[] = {
-	/*we don't need an exit table here, because there is only D3 cold on Kv*/
-	{
-	  .isFunctionNeededInRuntimeTable = phm_cf_want_uvd_power_gating,
-	  .tableFunction = cz_tf_uvd_power_gating_initialize
-	},
-	{
-	  .isFunctionNeededInRuntimeTable = phm_cf_want_vce_power_gating,
-	  .tableFunction = cz_tf_vce_power_gating_initialize
-	},
-	/* to do { NULL, cz_tf_xdma_power_gating_enable }, */
-	{ }
-};
-
-const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	cz_enable_clock_power_gatings_list
-};
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 7f3b24f..7efe008 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -440,14 +440,7 @@ static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
-					void *output, void *storage, int result)
-{
-	return 0;
-}
-
-static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
-				       void *output, void *storage, int result)
+static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
 {
 	struct SMU8_Fusion_ClkTable *clock_table;
 	int ret;
@@ -566,8 +559,7 @@ static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
 	return ret;
 }
 
-static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
-				 void *output, void *storage, int result)
+static int cz_init_sclk_limit(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 	struct phm_clock_voltage_dependency_table *table =
@@ -593,8 +585,7 @@ static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
 	return 0;
 }
 
-static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
-				void *output, void *storage, int result)
+static int cz_init_uvd_limit(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 	struct phm_uvd_clock_voltage_dependency_table *table =
@@ -621,8 +612,7 @@ static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
 	return 0;
 }
 
-static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
-				void *output, void *storage, int result)
+static int cz_init_vce_limit(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 	struct phm_vce_clock_voltage_dependency_table *table =
@@ -649,8 +639,7 @@ static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
 	return 0;
 }
 
-static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
-				void *output, void *storage, int result)
+static int cz_init_acp_limit(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 	struct phm_acp_clock_voltage_dependency_table *table =
@@ -676,8 +665,7 @@ static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
 	return 0;
 }
 
-static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
-				void *output, void *storage, int result)
+static void cz_init_power_gate_state(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 
@@ -686,22 +674,16 @@ static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
 	cz_hwmgr->samu_power_gated = false;
 	cz_hwmgr->acp_power_gated = false;
 	cz_hwmgr->pgacpinit = true;
-
-	return 0;
 }
 
-static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
-				void *output, void *storage, int result)
+static void cz_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 
 	cz_hwmgr->low_sclk_interrupt_threshold = 0;
-
-	return 0;
 }
-static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
-					void *input, void *output,
-					void *storage, int result)
+
+static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 	struct phm_clock_voltage_dependency_table *table =
@@ -774,9 +756,7 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
-					void *input, void *output,
-					void *storage, int result)
+static int cz_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr)
 {
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 				PHM_PlatformCaps_SclkDeepSleep)) {
@@ -794,9 +774,7 @@ static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
-					void *input, void *output,
-					void *storage, int result)
+static int cz_set_watermark_threshold(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *cz_hwmgr =
 				  (struct cz_hwmgr *)(hwmgr->backend);
@@ -808,63 +786,72 @@ static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
-					void *input, void *output,
-					void *storage, int result)
+static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
 {
+	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+
+	if (hw_data->is_nb_dpm_enabled) {
+		if (enable) {
+			PP_DBG_LOG("enable Low Memory PState.\n");
+
+			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+						PPSMC_MSG_EnableLowMemoryPstate,
+						(lock ? 1 : 0));
+		} else {
+			PP_DBG_LOG("disable Low Memory PState.\n");
+
+			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+						PPSMC_MSG_DisableLowMemoryPstate,
+						(lock ? 1 : 0));
+		}
+	}
+
 	return 0;
 }
 
-
-static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
-					void *input, void *output,
-					void *storage, int result)
+static int cz_disable_nb_dpm(struct pp_hwmgr *hwmgr)
 {
 	int ret = 0;
 
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 	unsigned long dpm_features = 0;
 
-	if (!cz_hwmgr->is_nb_dpm_enabled) {
-		PP_DBG_LOG("enabling ALL SMU features.\n");
+	if (cz_hwmgr->is_nb_dpm_enabled) {
+		cz_nbdpm_pstate_enable_disable(hwmgr, true, true);
 		dpm_features |= NB_DPM_MASK;
 		ret = smum_send_msg_to_smc_with_parameter(
 							  hwmgr->smumgr,
-							  PPSMC_MSG_EnableAllSmuFeatures,
+							  PPSMC_MSG_DisableAllSmuFeatures,
 							  dpm_features);
 		if (ret == 0)
-			cz_hwmgr->is_nb_dpm_enabled = true;
+			cz_hwmgr->is_nb_dpm_enabled = false;
 	}
 
 	return ret;
 }
 
-static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
+static int cz_enable_nb_dpm(struct pp_hwmgr *hwmgr)
 {
-	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
-
-	if (hw_data->is_nb_dpm_enabled) {
-		if (enable) {
-			PP_DBG_LOG("enable Low Memory PState.\n");
+	int ret = 0;
 
-			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-						PPSMC_MSG_EnableLowMemoryPstate,
-						(lock ? 1 : 0));
-		} else {
-			PP_DBG_LOG("disable Low Memory PState.\n");
+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+	unsigned long dpm_features = 0;
 
-			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-						PPSMC_MSG_DisableLowMemoryPstate,
-						(lock ? 1 : 0));
-		}
+	if (!cz_hwmgr->is_nb_dpm_enabled) {
+		PP_DBG_LOG("enabling ALL SMU features.\n");
+		dpm_features |= NB_DPM_MASK;
+		ret = smum_send_msg_to_smc_with_parameter(
+							  hwmgr->smumgr,
+							  PPSMC_MSG_EnableAllSmuFeatures,
+							  dpm_features);
+		if (ret == 0)
+			cz_hwmgr->is_nb_dpm_enabled = true;
 	}
 
-	return 0;
+	return ret;
 }
 
-static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
-					void *input, void *output,
-					void *storage, int result)
+static int cz_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input)
 {
 	bool disable_switch;
 	bool enable_low_mem_state;
@@ -886,64 +873,64 @@ static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-static const struct phm_master_table_item cz_set_power_state_list[] = {
-	{ .tableFunction = cz_tf_update_sclk_limit },
-	{ .tableFunction = cz_tf_set_deep_sleep_sclk_threshold },
-	{ .tableFunction = cz_tf_set_watermark_threshold },
-	{ .tableFunction = cz_tf_set_enabled_levels },
-	{ .tableFunction = cz_tf_enable_nb_dpm },
-	{ .tableFunction = cz_tf_update_low_mem_pstate },
-	{ }
-};
+static int cz_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
+{
+	int ret = 0;
 
-static const struct phm_master_table_header cz_set_power_state_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	cz_set_power_state_list
-};
+	cz_update_sclk_limit(hwmgr);
+	cz_set_deep_sleep_sclk_threshold(hwmgr);
+	cz_set_watermark_threshold(hwmgr);
+	ret = cz_enable_nb_dpm(hwmgr);
+	if (ret)
+		return ret;
+	cz_update_low_mem_pstate(hwmgr, input);
 
-static const struct phm_master_table_item cz_setup_asic_list[] = {
-	{ .tableFunction = cz_tf_reset_active_process_mask },
-	{ .tableFunction = cz_tf_upload_pptable_to_smu },
-	{ .tableFunction = cz_tf_init_sclk_limit },
-	{ .tableFunction = cz_tf_init_uvd_limit },
-	{ .tableFunction = cz_tf_init_vce_limit },
-	{ .tableFunction = cz_tf_init_acp_limit },
-	{ .tableFunction = cz_tf_init_power_gate_state },
-	{ .tableFunction = cz_tf_init_sclk_threshold },
-	{ }
+	return 0;
 };
 
-static const struct phm_master_table_header cz_setup_asic_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	cz_setup_asic_list
-};
 
-static int cz_tf_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr,
-					void *input, void *output,
-					void *storage, int result)
+static int cz_setup_asic_task(struct pp_hwmgr *hwmgr)
+{
+	int ret;
+
+	ret = cz_upload_pptable_to_smu(hwmgr);
+	if (ret)
+		return ret;
+	ret = cz_init_sclk_limit(hwmgr);
+	if (ret)
+		return ret;
+	ret = cz_init_uvd_limit(hwmgr);
+	if (ret)
+		return ret;
+	ret = cz_init_vce_limit(hwmgr);
+	if (ret)
+		return ret;
+	ret = cz_init_acp_limit(hwmgr);
+	if (ret)
+		return ret;
+
+	cz_init_power_gate_state(hwmgr);
+	cz_init_sclk_threshold(hwmgr);
+
+	return 0;
+}
+
+static void cz_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+
 	hw_data->disp_clk_bypass_pending = false;
 	hw_data->disp_clk_bypass = false;
-
-	return 0;
 }
 
-static int cz_tf_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr,
-					void *input, void *output,
-					void *storage, int result)
+static void cz_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
-	hw_data->is_nb_dpm_enabled = false;
 
-	return 0;
+	hw_data->is_nb_dpm_enabled = false;
 }
 
-static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
-					void *input, void *output,
-					void *storage, int result)
+static void cz_reset_cc6_data(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 
@@ -951,50 +938,60 @@ static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
 	hw_data->cc6_settings.cpu_pstate_separation_time = 0;
 	hw_data->cc6_settings.cpu_cc6_disable = false;
 	hw_data->cc6_settings.cpu_pstate_disable = false;
-
-	return 0;
 }
 
-static const struct phm_master_table_item cz_power_down_asic_list[] = {
-	{ .tableFunction = cz_tf_power_up_display_clock_sys_pll },
-	{ .tableFunction = cz_tf_clear_nb_dpm_flag },
-	{ .tableFunction = cz_tf_reset_cc6_data },
-	{ }
-};
-
-static const struct phm_master_table_header cz_power_down_asic_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	cz_power_down_asic_list
+static int cz_power_off_asic(struct pp_hwmgr *hwmgr)
+{
+	cz_power_up_display_clock_sys_pll(hwmgr);
+	cz_clear_nb_dpm_flag(hwmgr);
+	cz_reset_cc6_data(hwmgr);
+	return 0;
 };
 
-static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
-				void *output, void *storage, int result)
+static void cz_program_voting_clients(struct pp_hwmgr *hwmgr)
 {
 	PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
 				PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
-	return 0;
 }
 
-static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output,
-			   void *storage, int result)
+static void cz_clear_voting_clients(struct pp_hwmgr *hwmgr)
+{
+	PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0, 0);
+}
+
+static int cz_start_dpm(struct pp_hwmgr *hwmgr)
 {
-	int res = 0xff;
+	int ret = 0;
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 	unsigned long dpm_features = 0;
 
 	cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
 	dpm_features |= SCLK_DPM_MASK;
 
-	res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+	ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 				PPSMC_MSG_EnableAllSmuFeatures,
 				dpm_features);
 
-	return res;
+	return ret;
+}
+
+static int cz_stop_dpm(struct pp_hwmgr *hwmgr)
+{
+	int ret = 0;
+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+	unsigned long dpm_features = 0;
+
+	if (cz_hwmgr->dpm_flags & DPMFlags_SCLK_Enabled) {
+		dpm_features |= SCLK_DPM_MASK;
+		cz_hwmgr->dpm_flags &= ~DPMFlags_SCLK_Enabled;
+		ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+					PPSMC_MSG_DisableAllSmuFeatures,
+					dpm_features);
+	}
+	return ret;
 }
 
-static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
-				void *output, void *storage, int result)
+static int cz_program_bootup_state(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 
@@ -1016,13 +1013,11 @@ static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
 	return 0;
 }
 
-static int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
-				void *output, void *storage, int result)
+static void cz_reset_acp_boot_level(struct pp_hwmgr *hwmgr)
 {
 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 
 	cz_hwmgr->acp_boot_level = 0xff;
-	return 0;
 }
 
 static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
@@ -1038,60 +1033,45 @@ static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
 			return true;
 	}
 
-	return result;
+	return false;
 }
 
-static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input,
-				void *output, void *storage, int result)
+static bool cz_check_for_dpm_enabled(struct pp_hwmgr *hwmgr)
 {
 	if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
-		return PP_Result_TableImmediateExit;
-	return 0;
+		return true;
+	return false;
 }
 
-static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input,
-				void *output, void *storage, int result)
+static int cz_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
 {
-	/* TO DO */
-	return 0;
-}
+	if (!cz_check_for_dpm_enabled(hwmgr)) {
+		pr_info("dpm has been disabled\n");
+		return 0;
+	}
+	cz_disable_nb_dpm(hwmgr);
 
-static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
-						void *input, void *output,
-						void *storage, int result)
-{
-	if (!cz_dpm_check_smu_features(hwmgr,
-			     SMU_EnabledFeatureScoreboard_SclkDpmOn))
-		return PP_Result_TableImmediateExit;
-	return 0;
-}
+	cz_clear_voting_clients(hwmgr);
+	if (cz_stop_dpm(hwmgr))
+		return -EINVAL;
 
-static const struct phm_master_table_item cz_disable_dpm_list[] = {
-	{ .tableFunction = cz_tf_check_for_dpm_enabled },
-	{ },
+	return 0;
 };
 
+static int cz_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
+{
+	if (cz_check_for_dpm_enabled(hwmgr)) {
+		pr_info("dpm has been enabled\n");
+		return 0;
+	}
 
-static const struct phm_master_table_header cz_disable_dpm_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	cz_disable_dpm_list
-};
-
-static const struct phm_master_table_item cz_enable_dpm_list[] = {
-	{ .tableFunction = cz_tf_check_for_dpm_disabled },
-	{ .tableFunction = cz_tf_program_voting_clients },
-	{ .tableFunction = cz_tf_start_dpm },
-	{ .tableFunction = cz_tf_program_bootup_state },
-	{ .tableFunction = cz_tf_enable_didt },
-	{ .tableFunction = cz_tf_reset_acp_boot_level },
-	{ },
-};
+	cz_program_voting_clients(hwmgr);
+	if (cz_start_dpm(hwmgr))
+		return -EINVAL;
+	cz_program_bootup_state(hwmgr);
+	cz_reset_acp_boot_level(hwmgr);
 
-static const struct phm_master_table_header cz_enable_dpm_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	cz_enable_dpm_list
+	return 0;
 };
 
 static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
@@ -1162,7 +1142,8 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 		return -ENOMEM;
 
 	hwmgr->backend = data;
-
+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+			PHM_PlatformCaps_TablelessHardwareInterface);
 	result = cz_initialize_dpm_defaults(hwmgr);
 	if (result != 0) {
 		pr_err("cz_initialize_dpm_defaults failed\n");
@@ -1177,58 +1158,14 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 
 	cz_construct_boot_state(hwmgr);
 
-	result = phm_construct_table(hwmgr, &cz_setup_asic_master,
-				&(hwmgr->setup_asic));
-	if (result != 0) {
-		pr_err("Fail to construct setup ASIC\n");
-		return result;
-	}
-
-	result = phm_construct_table(hwmgr, &cz_power_down_asic_master,
-				&(hwmgr->power_down_asic));
-	if (result != 0) {
-		pr_err("Fail to construct power down ASIC\n");
-		return result;
-	}
-
-	result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
-				&(hwmgr->disable_dynamic_state_management));
-	if (result != 0) {
-		pr_err("Fail to disable_dynamic_state\n");
-		return result;
-	}
-	result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
-				&(hwmgr->enable_dynamic_state_management));
-	if (result != 0) {
-		pr_err("Fail to enable_dynamic_state\n");
-		return result;
-	}
-	result = phm_construct_table(hwmgr, &cz_set_power_state_master,
-				&(hwmgr->set_power_state));
-	if (result != 0) {
-		pr_err("Fail to construct set_power_state\n");
-		return result;
-	}
 	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =  CZ_MAX_HARDWARE_POWERLEVELS;
 
-	result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
-	if (result != 0) {
-		pr_err("Fail to construct enable_clock_power_gatings\n");
-		return result;
-	}
 	return result;
 }
 
 static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 {
 	if (hwmgr != NULL) {
-		phm_destroy_table(hwmgr, &(hwmgr->enable_clock_power_gatings));
-		phm_destroy_table(hwmgr, &(hwmgr->set_power_state));
-		phm_destroy_table(hwmgr, &(hwmgr->enable_dynamic_state_management));
-		phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management));
-		phm_destroy_table(hwmgr, &(hwmgr->power_down_asic));
-		phm_destroy_table(hwmgr, &(hwmgr->setup_asic));
-
 		kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
 		hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
 
@@ -1938,7 +1875,6 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 static const struct pp_hwmgr_func cz_hwmgr_funcs = {
 	.backend_init = cz_hwmgr_backend_init,
 	.backend_fini = cz_hwmgr_backend_fini,
-	.asic_setup = NULL,
 	.apply_state_adjust_rules = cz_apply_state_adjust_rules,
 	.force_dpm_level = cz_dpm_force_dpm_level,
 	.get_power_state_size = cz_get_power_state_size,
@@ -1960,6 +1896,11 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 	.get_clock_by_type = cz_get_clock_by_type,
 	.get_max_high_clocks = cz_get_max_high_clocks,
 	.read_sensor = cz_read_sensor,
+	.power_off_asic = cz_power_off_asic,
+	.asic_setup = cz_setup_asic_task,
+	.dynamic_state_management_enable = cz_enable_dpm_tasks,
+	.power_state_set = cz_set_power_state_tasks,
+	.dynamic_state_management_disable = cz_disable_dpm_tasks,
 };
 
 int cz_init_function_pointers(struct pp_hwmgr *hwmgr)
-- 
1.9.1

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Re: [PATCH 2/4] drm/amd/powerplay: refine powerplay code for CZ/ST

[Flora Cui]

On Tue, Sep 05, 2017 at 09:29:26AM +0800, Rex Zhu wrote:
> 1. add function points instand of creat function tables
> 2. implement stop dpm tasks for CZ/ST
better to split to 2 patches.

> 
> Change-Id: Ibe6fc92b989ba125da34857ce8b056e8b699b41b
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>  .../drm/amd/powerplay/hwmgr/cz_clockpowergating.c  |  30 --
>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     | 377 +++++++++------------
>  2 files changed, 159 insertions(+), 248 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
> index b33935f..5baf1a4 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
> @@ -103,16 +103,6 @@ int cz_phm_ungate_all_display_phys(struct pp_hwmgr *hwmgr)
>  	return 0;
>  }
>  
> -static int cz_tf_uvd_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result)
> -{
> -	return 0;
> -}
> -
> -static int cz_tf_vce_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result)
> -{
> -	return 0;
> -}
> -
>  int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
>  {
>  	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
> @@ -221,23 +211,3 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
>  	return 0;
>  }
>  
> -
> -static const struct phm_master_table_item cz_enable_clock_power_gatings_list[] = {
> -	/*we don't need an exit table here, because there is only D3 cold on Kv*/
> -	{
> -	  .isFunctionNeededInRuntimeTable = phm_cf_want_uvd_power_gating,
> -	  .tableFunction = cz_tf_uvd_power_gating_initialize
> -	},
> -	{
> -	  .isFunctionNeededInRuntimeTable = phm_cf_want_vce_power_gating,
> -	  .tableFunction = cz_tf_vce_power_gating_initialize
> -	},
> -	/* to do { NULL, cz_tf_xdma_power_gating_enable }, */
> -	{ }
> -};
> -
> -const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master = {
> -	0,
> -	PHM_MasterTableFlag_None,
> -	cz_enable_clock_power_gatings_list
> -};
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index 7f3b24f..7efe008 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> @@ -440,14 +440,7 @@ static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
>  	return 0;
>  }
>  
> -static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
> -					void *output, void *storage, int result)
> -{
> -	return 0;
> -}
> -
> -static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
> -				       void *output, void *storage, int result)
> +static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
>  {
>  	struct SMU8_Fusion_ClkTable *clock_table;
>  	int ret;
> @@ -566,8 +559,7 @@ static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
>  	return ret;
>  }
>  
> -static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
> -				 void *output, void *storage, int result)
> +static int cz_init_sclk_limit(struct pp_hwmgr *hwmgr)
>  {
>  	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>  	struct phm_clock_voltage_dependency_table *table =
> @@ -593,8 +585,7 @@ static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
>  	return 0;
>  }
>  
> -static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
> -				void *output, void *storage, int result)
> +static int cz_init_uvd_limit(struct pp_hwmgr *hwmgr)
>  {
>  	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>  	struct phm_uvd_clock_voltage_dependency_table *table =
> @@ -621,8 +612,7 @@ static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
>  	return 0;
>  }
>  
> -static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
> -				void *output, void *storage, int result)
> +static int cz_init_vce_limit(struct pp_hwmgr *hwmgr)
>  {
>  	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>  	struct phm_vce_clock_voltage_dependency_table *table =
> @@ -649,8 +639,7 @@ static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
>  	return 0;
>  }
>  
> -static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
> -				void *output, void *storage, int result)
> +static int cz_init_acp_limit(struct pp_hwmgr *hwmgr)
>  {
>  	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>  	struct phm_acp_clock_voltage_dependency_table *table =
> @@ -676,8 +665,7 @@ static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
>  	return 0;
>  }
>  
> -static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
> -				void *output, void *storage, int result)
> +static void cz_init_power_gate_state(struct pp_hwmgr *hwmgr)
>  {
>  	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>  
> @@ -686,22 +674,16 @@ static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
>  	cz_hwmgr->samu_power_gated = false;
>  	cz_hwmgr->acp_power_gated = false;
>  	cz_hwmgr->pgacpinit = true;
> -
> -	return 0;
>  }
>  
> -static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
> -				void *output, void *storage, int result)
> +static void cz_init_sclk_threshold(struct pp_hwmgr *hwmgr)
>  {
>  	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>  
>  	cz_hwmgr->low_sclk_interrupt_threshold = 0;
> -
> -	return 0;
>  }
> -static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
> -					void *input, void *output,
> -					void *storage, int result)
> +
> +static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
>  {
>  	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>  	struct phm_clock_voltage_dependency_table *table =
> @@ -774,9 +756,7 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
>  	return 0;
>  }
>  
> -static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
> -					void *input, void *output,
> -					void *storage, int result)
> +static int cz_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr)
>  {
>  	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>  				PHM_PlatformCaps_SclkDeepSleep)) {
> @@ -794,9 +774,7 @@ static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
>  	return 0;
>  }
>  
> -static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
> -					void *input, void *output,
> -					void *storage, int result)
> +static int cz_set_watermark_threshold(struct pp_hwmgr *hwmgr)
>  {
>  	struct cz_hwmgr *cz_hwmgr =
>  				  (struct cz_hwmgr *)(hwmgr->backend);
> @@ -808,63 +786,72 @@ static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
>  	return 0;
>  }
>  
> -static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
> -					void *input, void *output,
> -					void *storage, int result)
> +static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
>  {
> +	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
> +
> +	if (hw_data->is_nb_dpm_enabled) {
> +		if (enable) {
> +			PP_DBG_LOG("enable Low Memory PState.\n");
> +
> +			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
> +						PPSMC_MSG_EnableLowMemoryPstate,
> +						(lock ? 1 : 0));
> +		} else {
> +			PP_DBG_LOG("disable Low Memory PState.\n");
> +
> +			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
> +						PPSMC_MSG_DisableLowMemoryPstate,
> +						(lock ? 1 : 0));
> +		}
> +	}
> +
>  	return 0;
>  }
>  
> -
> -static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
> -					void *input, void *output,
> -					void *storage, int result)
> +static int cz_disable_nb_dpm(struct pp_hwmgr *hwmgr)
>  {
>  	int ret = 0;
>  
>  	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>  	unsigned long dpm_features = 0;
>  
> -	if (!cz_hwmgr->is_nb_dpm_enabled) {
> -		PP_DBG_LOG("enabling ALL SMU features.\n");
> +	if (cz_hwmgr->is_nb_dpm_enabled) {
> +		cz_nbdpm_pstate_enable_disable(hwmgr, true, true);
>  		dpm_features |= NB_DPM_MASK;
>  		ret = smum_send_msg_to_smc_with_parameter(
>  							  hwmgr->smumgr,
> -							  PPSMC_MSG_EnableAllSmuFeatures,
> +							  PPSMC_MSG_DisableAllSmuFeatures,
>  							  dpm_features);
>  		if (ret == 0)
> -			cz_hwmgr->is_nb_dpm_enabled = true;
> +			cz_hwmgr->is_nb_dpm_enabled = false;
>  	}
>  
>  	return ret;
>  }
>  
> -static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
> +static int cz_enable_nb_dpm(struct pp_hwmgr *hwmgr)
>  {
> -	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
> -
> -	if (hw_data->is_nb_dpm_enabled) {
> -		if (enable) {
> -			PP_DBG_LOG("enable Low Memory PState.\n");
> +	int ret = 0;
>  
> -			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
> -						PPSMC_MSG_EnableLowMemoryPstate,
> -						(lock ? 1 : 0));
> -		} else {
> -			PP_DBG_LOG("disable Low Memory PState.\n");
> +	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
> +	unsigned long dpm_features = 0;
>  
> -			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
> -						PPSMC_MSG_DisableLowMemoryPstate,
> -						(lock ? 1 : 0));
> -		}
> +	if (!cz_hwmgr->is_nb_dpm_enabled) {
> +		PP_DBG_LOG("enabling ALL SMU features.\n");
> +		dpm_features |= NB_DPM_MASK;
> +		ret = smum_send_msg_to_smc_with_parameter(
> +							  hwmgr->smumgr,
> +							  PPSMC_MSG_EnableAllSmuFeatures,
> +							  dpm_features);
> +		if (ret == 0)
> +			cz_hwmgr->is_nb_dpm_enabled = true;
>  	}
>  
> -	return 0;
> +	return ret;
>  }
>  
> -static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
> -					void *input, void *output,
> -					void *storage, int result)
> +static int cz_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input)
>  {
>  	bool disable_switch;
>  	bool enable_low_mem_state;
> @@ -886,64 +873,64 @@ static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
>  	return 0;
>  }
>  
> -static const struct phm_master_table_item cz_set_power_state_list[] = {
> -	{ .tableFunction = cz_tf_update_sclk_limit },
> -	{ .tableFunction = cz_tf_set_deep_sleep_sclk_threshold },
> -	{ .tableFunction = cz_tf_set_watermark_threshold },
> -	{ .tableFunction = cz_tf_set_enabled_levels },
> -	{ .tableFunction = cz_tf_enable_nb_dpm },
> -	{ .tableFunction = cz_tf_update_low_mem_pstate },
> -	{ }
> -};
> +static int cz_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
> +{
> +	int ret = 0;
>  
> -static const struct phm_master_table_header cz_set_power_state_master = {
> -	0,
> -	PHM_MasterTableFlag_None,
> -	cz_set_power_state_list
> -};
> +	cz_update_sclk_limit(hwmgr);
> +	cz_set_deep_sleep_sclk_threshold(hwmgr);
> +	cz_set_watermark_threshold(hwmgr);
> +	ret = cz_enable_nb_dpm(hwmgr);
> +	if (ret)
> +		return ret;
> +	cz_update_low_mem_pstate(hwmgr, input);
>  
> -static const struct phm_master_table_item cz_setup_asic_list[] = {
> -	{ .tableFunction = cz_tf_reset_active_process_mask },
> -	{ .tableFunction = cz_tf_upload_pptable_to_smu },
> -	{ .tableFunction = cz_tf_init_sclk_limit },
> -	{ .tableFunction = cz_tf_init_uvd_limit },
> -	{ .tableFunction = cz_tf_init_vce_limit },
> -	{ .tableFunction = cz_tf_init_acp_limit },
> -	{ .tableFunction = cz_tf_init_power_gate_state },
> -	{ .tableFunction = cz_tf_init_sclk_threshold },
> -	{ }
> +	return 0;
>  };
>  
> -static const struct phm_master_table_header cz_setup_asic_master = {
> -	0,
> -	PHM_MasterTableFlag_None,
> -	cz_setup_asic_list
> -};
>  
> -static int cz_tf_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr,
> -					void *input, void *output,
> -					void *storage, int result)
> +static int cz_setup_asic_task(struct pp_hwmgr *hwmgr)
> +{
> +	int ret;
> +
> +	ret = cz_upload_pptable_to_smu(hwmgr);
> +	if (ret)
> +		return ret;
> +	ret = cz_init_sclk_limit(hwmgr);
> +	if (ret)
> +		return ret;
> +	ret = cz_init_uvd_limit(hwmgr);
> +	if (ret)
> +		return ret;
> +	ret = cz_init_vce_limit(hwmgr);
> +	if (ret)
> +		return ret;
> +	ret = cz_init_acp_limit(hwmgr);
> +	if (ret)
> +		return ret;
> +
> +	cz_init_power_gate_state(hwmgr);
> +	cz_init_sclk_threshold(hwmgr);
> +
> +	return 0;
> +}
> +
> +static void cz_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr)
>  {
>  	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
> +
>  	hw_data->disp_clk_bypass_pending = false;
>  	hw_data->disp_clk_bypass = false;
> -
> -	return 0;
>  }
>  
> -static int cz_tf_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr,
> -					void *input, void *output,
> -					void *storage, int result)
> +static void cz_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr)
>  {
>  	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
> -	hw_data->is_nb_dpm_enabled = false;
>  
> -	return 0;
> +	hw_data->is_nb_dpm_enabled = false;
>  }
>  
> -static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
> -					void *input, void *output,
> -					void *storage, int result)
> +static void cz_reset_cc6_data(struct pp_hwmgr *hwmgr)
>  {
>  	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
>  
> @@ -951,50 +938,60 @@ static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
>  	hw_data->cc6_settings.cpu_pstate_separation_time = 0;
>  	hw_data->cc6_settings.cpu_cc6_disable = false;
>  	hw_data->cc6_settings.cpu_pstate_disable = false;
> -
> -	return 0;
>  }
>  
> -static const struct phm_master_table_item cz_power_down_asic_list[] = {
> -	{ .tableFunction = cz_tf_power_up_display_clock_sys_pll },
> -	{ .tableFunction = cz_tf_clear_nb_dpm_flag },
> -	{ .tableFunction = cz_tf_reset_cc6_data },
> -	{ }
> -};
> -
> -static const struct phm_master_table_header cz_power_down_asic_master = {
> -	0,
> -	PHM_MasterTableFlag_None,
> -	cz_power_down_asic_list
> +static int cz_power_off_asic(struct pp_hwmgr *hwmgr)
> +{
> +	cz_power_up_display_clock_sys_pll(hwmgr);
> +	cz_clear_nb_dpm_flag(hwmgr);
> +	cz_reset_cc6_data(hwmgr);
> +	return 0;
>  };
>  
> -static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
> -				void *output, void *storage, int result)
> +static void cz_program_voting_clients(struct pp_hwmgr *hwmgr)
>  {
>  	PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
>  				PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
> -	return 0;
>  }
>  
> -static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output,
> -			   void *storage, int result)
> +static void cz_clear_voting_clients(struct pp_hwmgr *hwmgr)
> +{
> +	PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0, 0);
> +}
> +
> +static int cz_start_dpm(struct pp_hwmgr *hwmgr)
>  {
> -	int res = 0xff;
> +	int ret = 0;
>  	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>  	unsigned long dpm_features = 0;
>  
>  	cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
>  	dpm_features |= SCLK_DPM_MASK;
>  
> -	res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
> +	ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
>  				PPSMC_MSG_EnableAllSmuFeatures,
>  				dpm_features);
>  
> -	return res;
> +	return ret;
> +}
> +
> +static int cz_stop_dpm(struct pp_hwmgr *hwmgr)
> +{
> +	int ret = 0;
> +	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
> +	unsigned long dpm_features = 0;
> +
> +	if (cz_hwmgr->dpm_flags & DPMFlags_SCLK_Enabled) {
> +		dpm_features |= SCLK_DPM_MASK;
> +		cz_hwmgr->dpm_flags &= ~DPMFlags_SCLK_Enabled;
> +		ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
> +					PPSMC_MSG_DisableAllSmuFeatures,
> +					dpm_features);
> +	}
> +	return ret;
>  }
>  
> -static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
> -				void *output, void *storage, int result)
> +static int cz_program_bootup_state(struct pp_hwmgr *hwmgr)
>  {
>  	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>  
> @@ -1016,13 +1013,11 @@ static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
>  	return 0;
>  }
>  
> -static int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
> -				void *output, void *storage, int result)
> +static void cz_reset_acp_boot_level(struct pp_hwmgr *hwmgr)
>  {
>  	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
>  
>  	cz_hwmgr->acp_boot_level = 0xff;
> -	return 0;
>  }
>  
>  static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
> @@ -1038,60 +1033,45 @@ static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
>  			return true;
>  	}
>  
> -	return result;
> +	return false;
>  }
>  
> -static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input,
> -				void *output, void *storage, int result)
> +static bool cz_check_for_dpm_enabled(struct pp_hwmgr *hwmgr)
>  {
>  	if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
> -		return PP_Result_TableImmediateExit;
> -	return 0;
> +		return true;
> +	return false;
>  }
>  
> -static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input,
> -				void *output, void *storage, int result)
> +static int cz_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
>  {
> -	/* TO DO */
> -	return 0;
> -}
> +	if (!cz_check_for_dpm_enabled(hwmgr)) {
> +		pr_info("dpm has been disabled\n");
> +		return 0;
> +	}
> +	cz_disable_nb_dpm(hwmgr);
>  
> -static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
> -						void *input, void *output,
> -						void *storage, int result)
> -{
> -	if (!cz_dpm_check_smu_features(hwmgr,
> -			     SMU_EnabledFeatureScoreboard_SclkDpmOn))
> -		return PP_Result_TableImmediateExit;
> -	return 0;
> -}
> +	cz_clear_voting_clients(hwmgr);
> +	if (cz_stop_dpm(hwmgr))
> +		return -EINVAL;
>  
> -static const struct phm_master_table_item cz_disable_dpm_list[] = {
> -	{ .tableFunction = cz_tf_check_for_dpm_enabled },
> -	{ },
> +	return 0;
>  };
>  
> +static int cz_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
> +{
> +	if (cz_check_for_dpm_enabled(hwmgr)) {
> +		pr_info("dpm has been enabled\n");
> +		return 0;
> +	}
>  
> -static const struct phm_master_table_header cz_disable_dpm_master = {
> -	0,
> -	PHM_MasterTableFlag_None,
> -	cz_disable_dpm_list
> -};
> -
> -static const struct phm_master_table_item cz_enable_dpm_list[] = {
> -	{ .tableFunction = cz_tf_check_for_dpm_disabled },
> -	{ .tableFunction = cz_tf_program_voting_clients },
> -	{ .tableFunction = cz_tf_start_dpm },
> -	{ .tableFunction = cz_tf_program_bootup_state },
> -	{ .tableFunction = cz_tf_enable_didt },
> -	{ .tableFunction = cz_tf_reset_acp_boot_level },
> -	{ },
> -};
> +	cz_program_voting_clients(hwmgr);
> +	if (cz_start_dpm(hwmgr))
> +		return -EINVAL;
> +	cz_program_bootup_state(hwmgr);
> +	cz_reset_acp_boot_level(hwmgr);
>  
> -static const struct phm_master_table_header cz_enable_dpm_master = {
> -	0,
> -	PHM_MasterTableFlag_None,
> -	cz_enable_dpm_list
> +	return 0;
>  };
>  
>  static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
> @@ -1162,7 +1142,8 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
>  		return -ENOMEM;
>  
>  	hwmgr->backend = data;
> -
> +	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> +			PHM_PlatformCaps_TablelessHardwareInterface);
>  	result = cz_initialize_dpm_defaults(hwmgr);
>  	if (result != 0) {
>  		pr_err("cz_initialize_dpm_defaults failed\n");
> @@ -1177,58 +1158,14 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
>  
>  	cz_construct_boot_state(hwmgr);
>  
> -	result = phm_construct_table(hwmgr, &cz_setup_asic_master,
> -				&(hwmgr->setup_asic));
> -	if (result != 0) {
> -		pr_err("Fail to construct setup ASIC\n");
> -		return result;
> -	}
> -
> -	result = phm_construct_table(hwmgr, &cz_power_down_asic_master,
> -				&(hwmgr->power_down_asic));
> -	if (result != 0) {
> -		pr_err("Fail to construct power down ASIC\n");
> -		return result;
> -	}
> -
> -	result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
> -				&(hwmgr->disable_dynamic_state_management));
> -	if (result != 0) {
> -		pr_err("Fail to disable_dynamic_state\n");
> -		return result;
> -	}
> -	result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
> -				&(hwmgr->enable_dynamic_state_management));
> -	if (result != 0) {
> -		pr_err("Fail to enable_dynamic_state\n");
> -		return result;
> -	}
> -	result = phm_construct_table(hwmgr, &cz_set_power_state_master,
> -				&(hwmgr->set_power_state));
> -	if (result != 0) {
> -		pr_err("Fail to construct set_power_state\n");
> -		return result;
> -	}
>  	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =  CZ_MAX_HARDWARE_POWERLEVELS;
>  
> -	result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
> -	if (result != 0) {
> -		pr_err("Fail to construct enable_clock_power_gatings\n");
> -		return result;
> -	}
>  	return result;
>  }
>  
>  static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
>  {
>  	if (hwmgr != NULL) {
> -		phm_destroy_table(hwmgr, &(hwmgr->enable_clock_power_gatings));
> -		phm_destroy_table(hwmgr, &(hwmgr->set_power_state));
> -		phm_destroy_table(hwmgr, &(hwmgr->enable_dynamic_state_management));
> -		phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management));
> -		phm_destroy_table(hwmgr, &(hwmgr->power_down_asic));
> -		phm_destroy_table(hwmgr, &(hwmgr->setup_asic));
> -
>  		kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
>  		hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
>  
> @@ -1938,7 +1875,6 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
>  static const struct pp_hwmgr_func cz_hwmgr_funcs = {
>  	.backend_init = cz_hwmgr_backend_init,
>  	.backend_fini = cz_hwmgr_backend_fini,
> -	.asic_setup = NULL,
>  	.apply_state_adjust_rules = cz_apply_state_adjust_rules,
>  	.force_dpm_level = cz_dpm_force_dpm_level,
>  	.get_power_state_size = cz_get_power_state_size,
> @@ -1960,6 +1896,11 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
>  	.get_clock_by_type = cz_get_clock_by_type,
>  	.get_max_high_clocks = cz_get_max_high_clocks,
>  	.read_sensor = cz_read_sensor,
> +	.power_off_asic = cz_power_off_asic,
> +	.asic_setup = cz_setup_asic_task,
> +	.dynamic_state_management_enable = cz_enable_dpm_tasks,
> +	.power_state_set = cz_set_power_state_tasks,
> +	.dynamic_state_management_disable = cz_disable_dpm_tasks,
>  };
>  
>  int cz_init_function_pointers(struct pp_hwmgr *hwmgr)
> -- 
> 1.9.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH 3/4] drm/amd/powerplay: refine powerplay code for RV

[Rex Zhu]

use function points instand of function table.

Change-Id: Ic3a4fc1492dcb33884c32a70ec9b2013b412d52a
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 137 ++++++-------------------
 1 file changed, 33 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index d5a9c07..da74f95 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -157,8 +157,7 @@ static int rv_construct_boot_state(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input,
-				void *output, void *storage, int result)
+static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
 {
 	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 	struct PP_Clocks clocks = {0};
@@ -234,19 +233,12 @@ static int rv_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
 	return 0;
 }
 
-static const struct phm_master_table_item rv_set_power_state_list[] = {
-	{ NULL, rv_tf_set_clock_limit },
-	{ }
-};
-
-static const struct phm_master_table_header rv_set_power_state_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	rv_set_power_state_list
-};
+static int rv_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
+{
+	return rv_set_clock_limit(hwmgr, input);
+}
 
-static int rv_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
-				void *output, void *storage, int result)
+static int rv_init_power_gate_state(struct pp_hwmgr *hwmgr)
 {
 	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 
@@ -257,20 +249,13 @@ static int rv_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
 	return 0;
 }
 
-static const struct phm_master_table_item rv_setup_asic_list[] = {
-	{ .tableFunction = rv_tf_init_power_gate_state },
-	{ }
-};
 
-static const struct phm_master_table_header rv_setup_asic_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	rv_setup_asic_list
-};
+static int rv_setup_asic_task(struct pp_hwmgr *hwmgr)
+{
+	return rv_init_power_gate_state(hwmgr);
+}
 
-static int rv_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
-					void *input, void *output,
-					void *storage, int result)
+static int rv_reset_cc6_data(struct pp_hwmgr *hwmgr)
 {
 	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 
@@ -282,21 +267,12 @@ static int rv_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-static const struct phm_master_table_item rv_power_down_asic_list[] = {
-	{ .tableFunction = rv_tf_reset_cc6_data },
-	{ }
-};
-
-static const struct phm_master_table_header rv_power_down_asic_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	rv_power_down_asic_list
-};
-
+static int rv_power_off_asic(struct pp_hwmgr *hwmgr)
+{
+	return rv_reset_cc6_data(hwmgr);
+}
 
-static int rv_tf_disable_gfx_off(struct pp_hwmgr *hwmgr,
-						void *input, void *output,
-						void *storage, int result)
+static int rv_disable_gfx_off(struct pp_hwmgr *hwmgr)
 {
 	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 
@@ -307,21 +283,12 @@ static int rv_tf_disable_gfx_off(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-static const struct phm_master_table_item rv_disable_dpm_list[] = {
-	{NULL, rv_tf_disable_gfx_off},
-	{ },
-};
-
-
-static const struct phm_master_table_header rv_disable_dpm_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	rv_disable_dpm_list
-};
+static int rv_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
+{
+	return rv_disable_gfx_off(hwmgr);
+}
 
-static int rv_tf_enable_gfx_off(struct pp_hwmgr *hwmgr,
-						void *input, void *output,
-						void *storage, int result)
+static int rv_enable_gfx_off(struct pp_hwmgr *hwmgr)
 {
 	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 
@@ -332,16 +299,10 @@ static int rv_tf_enable_gfx_off(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-static const struct phm_master_table_item rv_enable_dpm_list[] = {
-	{NULL, rv_tf_enable_gfx_off},
-	{ },
-};
-
-static const struct phm_master_table_header rv_enable_dpm_master = {
-	0,
-	PHM_MasterTableFlag_None,
-	rv_enable_dpm_list
-};
+static int rv_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
+{
+	return rv_enable_gfx_off(hwmgr);
+}
 
 static int rv_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 				struct pp_power_state  *prequest_ps,
@@ -474,6 +435,9 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 
 	hwmgr->backend = data;
 
+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+			PHM_PlatformCaps_TablelessHardwareInterface);
+
 	result = rv_initialize_dpm_defaults(hwmgr);
 	if (result != 0) {
 		pr_err("rv_initialize_dpm_defaults failed\n");
@@ -490,40 +454,6 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 
 	rv_construct_boot_state(hwmgr);
 
-	result = phm_construct_table(hwmgr, &rv_setup_asic_master,
-				&(hwmgr->setup_asic));
-	if (result != 0) {
-		pr_err("Fail to construct setup ASIC\n");
-		return result;
-	}
-
-	result = phm_construct_table(hwmgr, &rv_power_down_asic_master,
-				&(hwmgr->power_down_asic));
-	if (result != 0) {
-		pr_err("Fail to construct power down ASIC\n");
-		return result;
-	}
-
-	result = phm_construct_table(hwmgr, &rv_set_power_state_master,
-				&(hwmgr->set_power_state));
-	if (result != 0) {
-		pr_err("Fail to construct set_power_state\n");
-		return result;
-	}
-
-	result = phm_construct_table(hwmgr, &rv_disable_dpm_master,
-				&(hwmgr->disable_dynamic_state_management));
-	if (result != 0) {
-		pr_err("Fail to disable_dynamic_state\n");
-		return result;
-	}
-	result = phm_construct_table(hwmgr, &rv_enable_dpm_master,
-				&(hwmgr->enable_dynamic_state_management));
-	if (result != 0) {
-		pr_err("Fail to enable_dynamic_state\n");
-		return result;
-	}
-
 	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 						RAVEN_MAX_HARDWARE_POWERLEVELS;
 
@@ -546,12 +476,6 @@ static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 	struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
 
-	phm_destroy_table(hwmgr, &(hwmgr->set_power_state));
-	phm_destroy_table(hwmgr, &(hwmgr->enable_dynamic_state_management));
-	phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management));
-	phm_destroy_table(hwmgr, &(hwmgr->power_down_asic));
-	phm_destroy_table(hwmgr, &(hwmgr->setup_asic));
-
 	kfree(pinfo->vdd_dep_on_dcefclk);
 	pinfo->vdd_dep_on_dcefclk = NULL;
 	kfree(pinfo->vdd_dep_on_socclk);
@@ -946,6 +870,11 @@ static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 	.read_sensor = rv_read_sensor,
 	.set_active_display_count = rv_set_active_display_count,
 	.set_deep_sleep_dcefclk = rv_set_deep_sleep_dcefclk,
+	.dynamic_state_management_enable = rv_enable_dpm_tasks,
+	.power_off_asic = rv_power_off_asic,
+	.asic_setup = rv_setup_asic_task,
+	.power_state_set = rv_set_power_state_tasks,
+	.dynamic_state_management_disable = rv_disable_dpm_tasks,
 };
 
 int rv_init_function_pointers(struct pp_hwmgr *hwmgr)
-- 
1.9.1

_______________________________________________
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amd-gfx@lists.freedesktop.org
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[PATCH 4/4] drm/amd/powerplay: delete dead code in powerplay

[Rex Zhu]

delete functiontable related codes

Change-Id: If4bba21beaf3e7fe100eb80def28f83f3b8ef077
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/Makefile       |   2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     |   3 +-
 .../gpu/drm/amd/powerplay/hwmgr/functiontables.c   | 161 ---------------------
 .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  |  82 +++--------
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        |  12 --
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c     |   3 -
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |   3 -
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |  48 ------
 8 files changed, 22 insertions(+), 292 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index 79119d6..dc4bbcf 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the 'hw manager' sub-component of powerplay.
 # It provides the hardware management services for the driver.
 
-HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
+HARDWARE_MGR = hwmgr.o processpptables.o \
 		hardwaremanager.o pp_acpi.o cz_hwmgr.o \
 		cz_clockpowergating.o pppcielanes.o\
 		process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 7efe008..d3b4646 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1142,8 +1142,7 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 		return -ENOMEM;
 
 	hwmgr->backend = data;
-	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-			PHM_PlatformCaps_TablelessHardwareInterface);
+
 	result = cz_initialize_dpm_defaults(hwmgr);
 	if (result != 0) {
 		pr_err("cz_initialize_dpm_defaults failed\n");
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
deleted file mode 100644
index bc7d8bd..0000000
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include "hwmgr.h"
-
-static int phm_run_table(struct pp_hwmgr *hwmgr,
-			 struct phm_runtime_table_header *rt_table,
-			 void *input,
-			 void *output,
-			 void *temp_storage)
-{
-	int result = 0;
-	phm_table_function *function;
-
-	if (rt_table->function_list == NULL) {
-		pr_debug("this function not implement!\n");
-		return 0;
-	}
-
-	for (function = rt_table->function_list; NULL != *function; function++) {
-		int tmp = (*function)(hwmgr, input, output, temp_storage, result);
-
-		if (tmp == PP_Result_TableImmediateExit)
-			break;
-		if (tmp) {
-			if (0 == result)
-				result = tmp;
-			if (rt_table->exit_error)
-				break;
-		}
-	}
-
-	return result;
-}
-
-int phm_dispatch_table(struct pp_hwmgr *hwmgr,
-		       struct phm_runtime_table_header *rt_table,
-		       void *input, void *output)
-{
-	int result;
-	void *temp_storage;
-
-	if (hwmgr == NULL || rt_table == NULL) {
-		pr_err("Invalid Parameter!\n");
-		return -EINVAL;
-	}
-
-	if (0 != rt_table->storage_size) {
-		temp_storage = kzalloc(rt_table->storage_size, GFP_KERNEL);
-		if (temp_storage == NULL) {
-			pr_err("Could not allocate table temporary storage\n");
-			return -ENOMEM;
-		}
-	} else {
-		temp_storage = NULL;
-	}
-
-	result = phm_run_table(hwmgr, rt_table, input, output, temp_storage);
-
-	kfree(temp_storage);
-
-	return result;
-}
-
-int phm_construct_table(struct pp_hwmgr *hwmgr,
-			const struct phm_master_table_header *master_table,
-			struct phm_runtime_table_header *rt_table)
-{
-	uint32_t function_count = 0;
-	const struct phm_master_table_item *table_item;
-	uint32_t size;
-	phm_table_function *run_time_list;
-	phm_table_function *rtf;
-
-	if (hwmgr == NULL || master_table == NULL || rt_table == NULL) {
-		pr_err("Invalid Parameter!\n");
-		return -EINVAL;
-	}
-
-	for (table_item = master_table->master_list;
-		NULL != table_item->tableFunction; table_item++) {
-		if ((NULL == table_item->isFunctionNeededInRuntimeTable) ||
-		    (table_item->isFunctionNeededInRuntimeTable(hwmgr)))
-			function_count++;
-	}
-
-	size = (function_count + 1) * sizeof(phm_table_function);
-	run_time_list = kzalloc(size, GFP_KERNEL);
-
-	if (NULL == run_time_list)
-		return -ENOMEM;
-
-	rtf = run_time_list;
-	for (table_item = master_table->master_list;
-		NULL != table_item->tableFunction; table_item++) {
-		if ((rtf - run_time_list) > function_count) {
-			pr_err("Check function results have changed\n");
-			kfree(run_time_list);
-			return -EINVAL;
-		}
-
-		if ((NULL == table_item->isFunctionNeededInRuntimeTable) ||
-		     (table_item->isFunctionNeededInRuntimeTable(hwmgr))) {
-			*(rtf++) = table_item->tableFunction;
-		}
-	}
-
-	if ((rtf - run_time_list) > function_count) {
-		pr_err("Check function results have changed\n");
-		kfree(run_time_list);
-		return -EINVAL;
-	}
-
-	*rtf = NULL;
-	rt_table->function_list = run_time_list;
-	rt_table->exit_error = (0 != (master_table->flags & PHM_MasterTableFlag_ExitOnError));
-	rt_table->storage_size = master_table->storage_size;
-	return 0;
-}
-
-int phm_destroy_table(struct pp_hwmgr *hwmgr,
-		      struct phm_runtime_table_header *rt_table)
-{
-	if (hwmgr == NULL || rt_table == NULL) {
-		pr_err("Invalid Parameter\n");
-		return -EINVAL;
-	}
-
-	if (NULL == rt_table->function_list)
-		return 0;
-
-	kfree(rt_table->function_list);
-
-	rt_table->function_list = NULL;
-	rt_table->storage_size = 0;
-	rt_table->exit_error = false;
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index a3991c0..d77753d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -51,14 +51,8 @@ int phm_setup_asic(struct pp_hwmgr *hwmgr)
 {
 	PHM_FUNC_CHECK(hwmgr);
 
-	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-		PHM_PlatformCaps_TablelessHardwareInterface)) {
-		if (NULL != hwmgr->hwmgr_func->asic_setup)
-			return hwmgr->hwmgr_func->asic_setup(hwmgr);
-	} else {
-		return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
-					  NULL, NULL);
-	}
+	if (NULL != hwmgr->hwmgr_func->asic_setup)
+		return hwmgr->hwmgr_func->asic_setup(hwmgr);
 
 	return 0;
 }
@@ -67,14 +61,8 @@ int phm_power_down_asic(struct pp_hwmgr *hwmgr)
 {
 	PHM_FUNC_CHECK(hwmgr);
 
-	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-		PHM_PlatformCaps_TablelessHardwareInterface)) {
-		if (NULL != hwmgr->hwmgr_func->power_off_asic)
-			return hwmgr->hwmgr_func->power_off_asic(hwmgr);
-	} else {
-		return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
-					  NULL, NULL);
-	}
+	if (NULL != hwmgr->hwmgr_func->power_off_asic)
+		return hwmgr->hwmgr_func->power_off_asic(hwmgr);
 
 	return 0;
 }
@@ -90,13 +78,8 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
 	states.pcurrent_state = pcurrent_state;
 	states.pnew_state = pnew_power_state;
 
-	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-		PHM_PlatformCaps_TablelessHardwareInterface)) {
-		if (NULL != hwmgr->hwmgr_func->power_state_set)
-			return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
-	} else {
-		return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
-	}
+	if (NULL != hwmgr->hwmgr_func->power_state_set)
+		return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
 
 	return 0;
 }
@@ -107,15 +90,8 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
 	bool enabled;
 	PHM_FUNC_CHECK(hwmgr);
 
-	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-		PHM_PlatformCaps_TablelessHardwareInterface)) {
-		if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
-			ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
-	} else {
-		ret = phm_dispatch_table(hwmgr,
-				&(hwmgr->enable_dynamic_state_management),
-				NULL, NULL);
-	}
+	if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
+		ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
 
 	enabled = ret == 0;
 
@@ -131,15 +107,8 @@ int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
 
 	PHM_FUNC_CHECK(hwmgr);
 
-	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-		PHM_PlatformCaps_TablelessHardwareInterface)) {
-		if (hwmgr->hwmgr_func->dynamic_state_management_disable)
-			ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
-	} else {
-		ret = phm_dispatch_table(hwmgr,
-				&(hwmgr->disable_dynamic_state_management),
-				NULL, NULL);
-	}
+	if (hwmgr->hwmgr_func->dynamic_state_management_disable)
+		ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
 
 	enabled = ret == 0 ? false : true;
 
@@ -219,13 +188,9 @@ int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
 {
 	PHM_FUNC_CHECK(hwmgr);
 
-	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-		PHM_PlatformCaps_TablelessHardwareInterface)) {
-		if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
-			return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
-	} else {
-		return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
-	}
+	if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
+		return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
+
 	return 0;
 }
 
@@ -233,11 +198,9 @@ int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
 {
 	PHM_FUNC_CHECK(hwmgr);
 
-	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-		PHM_PlatformCaps_TablelessHardwareInterface)) {
-		if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
-			return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
-	}
+	if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
+		return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
+
 	return 0;
 }
 
@@ -246,12 +209,9 @@ int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
 {
 	PHM_FUNC_CHECK(hwmgr);
 
-	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-				 PHM_PlatformCaps_TablelessHardwareInterface)) {
-		if (NULL != hwmgr->hwmgr_func->display_config_changed)
-			hwmgr->hwmgr_func->display_config_changed(hwmgr);
-	} else
-		return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
+	if (NULL != hwmgr->hwmgr_func->display_config_changed)
+		hwmgr->hwmgr_func->display_config_changed(hwmgr);
+
 	return 0;
 }
 
@@ -259,9 +219,7 @@ int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
 {
 	PHM_FUNC_CHECK(hwmgr);
 
-	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-				 PHM_PlatformCaps_TablelessHardwareInterface))
-		if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
+	if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
 			hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
 
 	return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index f0d0d1f..7ae26f5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -852,10 +852,6 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 					PHM_PlatformCaps_AutomaticDCTransition);
 
-	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-				PHM_PlatformCaps_TablelessHardwareInterface);
-
-
 	if (hwmgr->chip_id != CHIP_POLARIS10)
 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 					PHM_PlatformCaps_SPLLShutdownSupport);
@@ -882,9 +878,6 @@ int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_TCPRamping);
 
-	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-			PHM_PlatformCaps_TablelessHardwareInterface);
-
 	return 0;
 }
 
@@ -904,9 +897,6 @@ int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 		      PHM_PlatformCaps_VCEPowerGating);
 
-	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-			 PHM_PlatformCaps_TablelessHardwareInterface);
-
 	return 0;
 }
 
@@ -921,8 +911,6 @@ int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_TCPRamping);
 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-			 PHM_PlatformCaps_TablelessHardwareInterface);
-	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 		    PHM_PlatformCaps_EVV);
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index da74f95..594b978 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -435,9 +435,6 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 
 	hwmgr->backend = data;
 
-	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-			PHM_PlatformCaps_TablelessHardwareInterface);
-
 	result = rv_initialize_dpm_defaults(hwmgr);
 	if (result != 0) {
 		pr_err("rv_initialize_dpm_defaults failed\n");
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index e5f530b..b7a789f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -200,9 +200,6 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 				PHM_PlatformCaps_ControlVDDCI);
 
 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-			PHM_PlatformCaps_TablelessHardwareInterface);
-
-	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_EnableSMU7ThermalManagement);
 
 	sys_info.size = sizeof(struct cgs_system_info);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 831add4..5c1e6a7 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -109,10 +109,6 @@ enum PHM_BackEnd_Magic {
 #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE     2
 #define PHM_PCIE_POWERGATING_TARGET_PHY            3
 
-typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
-				  void *output, void *storage, int result);
-
-typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
 
 struct phm_set_power_state_input {
 	const struct pp_hw_power_state *pcurrent_state;
@@ -149,30 +145,6 @@ struct phm_gfx_arbiter {
 	uint32_t fclk;
 };
 
-/* Entries in the master tables */
-struct phm_master_table_item {
-	phm_check_function isFunctionNeededInRuntimeTable;
-	phm_table_function tableFunction;
-};
-
-enum phm_master_table_flag {
-	PHM_MasterTableFlag_None         = 0,
-	PHM_MasterTableFlag_ExitOnError  = 1,
-};
-
-/* The header of the master tables */
-struct phm_master_table_header {
-	uint32_t storage_size;
-	uint32_t flags;
-	const struct phm_master_table_item *master_list;
-};
-
-struct phm_runtime_table_header {
-	uint32_t storage_size;
-	bool exit_error;
-	phm_table_function *function_list;
-};
-
 struct phm_clock_array {
 	uint32_t count;
 	uint32_t values[1];
@@ -216,19 +188,6 @@ struct phm_phase_shedding_limits_record {
 	uint32_t    Mclk;
 };
 
-
-extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
-			      struct phm_runtime_table_header *rt_table,
-			      void *input, void *output);
-
-extern int phm_construct_table(struct pp_hwmgr *hwmgr,
-			       const struct phm_master_table_header *master_table,
-			       struct phm_runtime_table_header *rt_table);
-
-extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
-			     struct phm_runtime_table_header *rt_table);
-
-
 struct phm_uvd_clock_voltage_dependency_record {
 	uint32_t vclk;
 	uint32_t dclk;
@@ -760,13 +719,6 @@ struct pp_hwmgr {
 	void *backend;
 	enum PP_DAL_POWERLEVEL dal_power_level;
 	struct phm_dynamic_state_info dyn_state;
-	struct phm_runtime_table_header setup_asic;
-	struct phm_runtime_table_header power_down_asic;
-	struct phm_runtime_table_header disable_dynamic_state_management;
-	struct phm_runtime_table_header enable_dynamic_state_management;
-	struct phm_runtime_table_header set_power_state;
-	struct phm_runtime_table_header enable_clock_power_gatings;
-	struct phm_runtime_table_header display_configuration_changed;
 	const struct pp_hwmgr_func *hwmgr_func;
 	const struct pp_table_func *pptable_func;
 	struct pp_power_state    *ps;
-- 
1.9.1

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RE: [PATCH 4/4] drm/amd/powerplay: delete dead code in powerplay

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Monday, September 04, 2017 9:29 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 4/4] drm/amd/powerplay: delete dead code in powerplay
> 
> delete functiontable related codes
> 
> Change-Id: If4bba21beaf3e7fe100eb80def28f83f3b8ef077
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/Makefile       |   2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     |   3 +-
>  .../gpu/drm/amd/powerplay/hwmgr/functiontables.c   | 161 -------------------
> --
>  .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  |  82 +++--------
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        |  12 --
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c     |   3 -
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |   3 -
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |  48 ------
>  8 files changed, 22 insertions(+), 292 deletions(-)
>  delete mode 100644
> drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
> b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
> index 79119d6..dc4bbcf 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
> @@ -2,7 +2,7 @@
>  # Makefile for the 'hw manager' sub-component of powerplay.
>  # It provides the hardware management services for the driver.
> 
> -HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
> +HARDWARE_MGR = hwmgr.o processpptables.o \
>  		hardwaremanager.o pp_acpi.o cz_hwmgr.o \
>  		cz_clockpowergating.o pppcielanes.o\
>  		process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index 7efe008..d3b4646 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> @@ -1142,8 +1142,7 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr
> *hwmgr)
>  		return -ENOMEM;
> 
>  	hwmgr->backend = data;
> -	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> -			PHM_PlatformCaps_TablelessHardwareInterface);
> +
>  	result = cz_initialize_dpm_defaults(hwmgr);
>  	if (result != 0) {
>  		pr_err("cz_initialize_dpm_defaults failed\n");
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
> deleted file mode 100644
> index bc7d8bd..0000000
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
> +++ /dev/null
> @@ -1,161 +0,0 @@
> -/*
> - * Copyright 2015 Advanced Micro Devices, Inc.
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the
> "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> EVENT SHALL
> - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> DAMAGES OR
> - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
> THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - *
> - */
> -#include <linux/types.h>
> -#include <linux/kernel.h>
> -#include <linux/slab.h>
> -#include "hwmgr.h"
> -
> -static int phm_run_table(struct pp_hwmgr *hwmgr,
> -			 struct phm_runtime_table_header *rt_table,
> -			 void *input,
> -			 void *output,
> -			 void *temp_storage)
> -{
> -	int result = 0;
> -	phm_table_function *function;
> -
> -	if (rt_table->function_list == NULL) {
> -		pr_debug("this function not implement!\n");
> -		return 0;
> -	}
> -
> -	for (function = rt_table->function_list; NULL != *function;
> function++) {
> -		int tmp = (*function)(hwmgr, input, output, temp_storage,
> result);
> -
> -		if (tmp == PP_Result_TableImmediateExit)
> -			break;
> -		if (tmp) {
> -			if (0 == result)
> -				result = tmp;
> -			if (rt_table->exit_error)
> -				break;
> -		}
> -	}
> -
> -	return result;
> -}
> -
> -int phm_dispatch_table(struct pp_hwmgr *hwmgr,
> -		       struct phm_runtime_table_header *rt_table,
> -		       void *input, void *output)
> -{
> -	int result;
> -	void *temp_storage;
> -
> -	if (hwmgr == NULL || rt_table == NULL) {
> -		pr_err("Invalid Parameter!\n");
> -		return -EINVAL;
> -	}
> -
> -	if (0 != rt_table->storage_size) {
> -		temp_storage = kzalloc(rt_table->storage_size,
> GFP_KERNEL);
> -		if (temp_storage == NULL) {
> -			pr_err("Could not allocate table temporary
> storage\n");
> -			return -ENOMEM;
> -		}
> -	} else {
> -		temp_storage = NULL;
> -	}
> -
> -	result = phm_run_table(hwmgr, rt_table, input, output,
> temp_storage);
> -
> -	kfree(temp_storage);
> -
> -	return result;
> -}
> -
> -int phm_construct_table(struct pp_hwmgr *hwmgr,
> -			const struct phm_master_table_header
> *master_table,
> -			struct phm_runtime_table_header *rt_table)
> -{
> -	uint32_t function_count = 0;
> -	const struct phm_master_table_item *table_item;
> -	uint32_t size;
> -	phm_table_function *run_time_list;
> -	phm_table_function *rtf;
> -
> -	if (hwmgr == NULL || master_table == NULL || rt_table == NULL) {
> -		pr_err("Invalid Parameter!\n");
> -		return -EINVAL;
> -	}
> -
> -	for (table_item = master_table->master_list;
> -		NULL != table_item->tableFunction; table_item++) {
> -		if ((NULL == table_item->isFunctionNeededInRuntimeTable)
> ||
> -		    (table_item->isFunctionNeededInRuntimeTable(hwmgr)))
> -			function_count++;
> -	}
> -
> -	size = (function_count + 1) * sizeof(phm_table_function);
> -	run_time_list = kzalloc(size, GFP_KERNEL);
> -
> -	if (NULL == run_time_list)
> -		return -ENOMEM;
> -
> -	rtf = run_time_list;
> -	for (table_item = master_table->master_list;
> -		NULL != table_item->tableFunction; table_item++) {
> -		if ((rtf - run_time_list) > function_count) {
> -			pr_err("Check function results have changed\n");
> -			kfree(run_time_list);
> -			return -EINVAL;
> -		}
> -
> -		if ((NULL == table_item->isFunctionNeededInRuntimeTable)
> ||
> -		     (table_item->isFunctionNeededInRuntimeTable(hwmgr)))
> {
> -			*(rtf++) = table_item->tableFunction;
> -		}
> -	}
> -
> -	if ((rtf - run_time_list) > function_count) {
> -		pr_err("Check function results have changed\n");
> -		kfree(run_time_list);
> -		return -EINVAL;
> -	}
> -
> -	*rtf = NULL;
> -	rt_table->function_list = run_time_list;
> -	rt_table->exit_error = (0 != (master_table->flags &
> PHM_MasterTableFlag_ExitOnError));
> -	rt_table->storage_size = master_table->storage_size;
> -	return 0;
> -}
> -
> -int phm_destroy_table(struct pp_hwmgr *hwmgr,
> -		      struct phm_runtime_table_header *rt_table)
> -{
> -	if (hwmgr == NULL || rt_table == NULL) {
> -		pr_err("Invalid Parameter\n");
> -		return -EINVAL;
> -	}
> -
> -	if (NULL == rt_table->function_list)
> -		return 0;
> -
> -	kfree(rt_table->function_list);
> -
> -	rt_table->function_list = NULL;
> -	rt_table->storage_size = 0;
> -	rt_table->exit_error = false;
> -
> -	return 0;
> -}
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> index a3991c0..d77753d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> @@ -51,14 +51,8 @@ int phm_setup_asic(struct pp_hwmgr *hwmgr)
>  {
>  	PHM_FUNC_CHECK(hwmgr);
> 
> -	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> -		PHM_PlatformCaps_TablelessHardwareInterface)) {
> -		if (NULL != hwmgr->hwmgr_func->asic_setup)
> -			return hwmgr->hwmgr_func->asic_setup(hwmgr);
> -	} else {
> -		return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
> -					  NULL, NULL);
> -	}
> +	if (NULL != hwmgr->hwmgr_func->asic_setup)
> +		return hwmgr->hwmgr_func->asic_setup(hwmgr);
> 
>  	return 0;
>  }
> @@ -67,14 +61,8 @@ int phm_power_down_asic(struct pp_hwmgr
> *hwmgr)
>  {
>  	PHM_FUNC_CHECK(hwmgr);
> 
> -	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> -		PHM_PlatformCaps_TablelessHardwareInterface)) {
> -		if (NULL != hwmgr->hwmgr_func->power_off_asic)
> -			return hwmgr->hwmgr_func-
> >power_off_asic(hwmgr);
> -	} else {
> -		return phm_dispatch_table(hwmgr, &(hwmgr-
> >power_down_asic),
> -					  NULL, NULL);
> -	}
> +	if (NULL != hwmgr->hwmgr_func->power_off_asic)
> +		return hwmgr->hwmgr_func->power_off_asic(hwmgr);
> 
>  	return 0;
>  }
> @@ -90,13 +78,8 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
>  	states.pcurrent_state = pcurrent_state;
>  	states.pnew_state = pnew_power_state;
> 
> -	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> -		PHM_PlatformCaps_TablelessHardwareInterface)) {
> -		if (NULL != hwmgr->hwmgr_func->power_state_set)
> -			return hwmgr->hwmgr_func-
> >power_state_set(hwmgr, &states);
> -	} else {
> -		return phm_dispatch_table(hwmgr, &(hwmgr-
> >set_power_state), &states, NULL);
> -	}
> +	if (NULL != hwmgr->hwmgr_func->power_state_set)
> +		return hwmgr->hwmgr_func->power_state_set(hwmgr,
> &states);
> 
>  	return 0;
>  }
> @@ -107,15 +90,8 @@ int phm_enable_dynamic_state_management(struct
> pp_hwmgr *hwmgr)
>  	bool enabled;
>  	PHM_FUNC_CHECK(hwmgr);
> 
> -	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> -		PHM_PlatformCaps_TablelessHardwareInterface)) {
> -		if (NULL != hwmgr->hwmgr_func-
> >dynamic_state_management_enable)
> -			ret = hwmgr->hwmgr_func-
> >dynamic_state_management_enable(hwmgr);
> -	} else {
> -		ret = phm_dispatch_table(hwmgr,
> -				&(hwmgr-
> >enable_dynamic_state_management),
> -				NULL, NULL);
> -	}
> +	if (NULL != hwmgr->hwmgr_func-
> >dynamic_state_management_enable)
> +		ret = hwmgr->hwmgr_func-
> >dynamic_state_management_enable(hwmgr);
> 
>  	enabled = ret == 0;
> 
> @@ -131,15 +107,8 @@ int
> phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
> 
>  	PHM_FUNC_CHECK(hwmgr);
> 
> -	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> -		PHM_PlatformCaps_TablelessHardwareInterface)) {
> -		if (hwmgr->hwmgr_func-
> >dynamic_state_management_disable)
> -			ret = hwmgr->hwmgr_func-
> >dynamic_state_management_disable(hwmgr);
> -	} else {
> -		ret = phm_dispatch_table(hwmgr,
> -				&(hwmgr-
> >disable_dynamic_state_management),
> -				NULL, NULL);
> -	}
> +	if (hwmgr->hwmgr_func->dynamic_state_management_disable)
> +		ret = hwmgr->hwmgr_func-
> >dynamic_state_management_disable(hwmgr);
> 
>  	enabled = ret == 0 ? false : true;
> 
> @@ -219,13 +188,9 @@ int phm_enable_clock_power_gatings(struct
> pp_hwmgr *hwmgr)
>  {
>  	PHM_FUNC_CHECK(hwmgr);
> 
> -	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> -		PHM_PlatformCaps_TablelessHardwareInterface)) {
> -		if (NULL != hwmgr->hwmgr_func-
> >enable_clock_power_gating)
> -			return hwmgr->hwmgr_func-
> >enable_clock_power_gating(hwmgr);
> -	} else {
> -		return phm_dispatch_table(hwmgr, &(hwmgr-
> >enable_clock_power_gatings), NULL, NULL);
> -	}
> +	if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
> +		return hwmgr->hwmgr_func-
> >enable_clock_power_gating(hwmgr);
> +
>  	return 0;
>  }
> 
> @@ -233,11 +198,9 @@ int phm_disable_clock_power_gatings(struct
> pp_hwmgr *hwmgr)
>  {
>  	PHM_FUNC_CHECK(hwmgr);
> 
> -	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> -		PHM_PlatformCaps_TablelessHardwareInterface)) {
> -		if (NULL != hwmgr->hwmgr_func-
> >disable_clock_power_gating)
> -			return hwmgr->hwmgr_func-
> >disable_clock_power_gating(hwmgr);
> -	}
> +	if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
> +		return hwmgr->hwmgr_func-
> >disable_clock_power_gating(hwmgr);
> +
>  	return 0;
>  }
> 
> @@ -246,12 +209,9 @@ int phm_display_configuration_changed(struct
> pp_hwmgr *hwmgr)
>  {
>  	PHM_FUNC_CHECK(hwmgr);
> 
> -	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> -
> PHM_PlatformCaps_TablelessHardwareInterface)) {
> -		if (NULL != hwmgr->hwmgr_func->display_config_changed)
> -			hwmgr->hwmgr_func-
> >display_config_changed(hwmgr);
> -	} else
> -		return phm_dispatch_table(hwmgr, &hwmgr-
> >display_configuration_changed, NULL, NULL);
> +	if (NULL != hwmgr->hwmgr_func->display_config_changed)
> +		hwmgr->hwmgr_func->display_config_changed(hwmgr);
> +
>  	return 0;
>  }
> 
> @@ -259,9 +219,7 @@ int
> phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr
> *hwmgr)
>  {
>  	PHM_FUNC_CHECK(hwmgr);
> 
> -	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> -
> PHM_PlatformCaps_TablelessHardwareInterface))
> -		if (NULL != hwmgr->hwmgr_func-
> >notify_smc_display_config_after_ps_adjustment)
> +	if (NULL != hwmgr->hwmgr_func-
> >notify_smc_display_config_after_ps_adjustment)
>  			hwmgr->hwmgr_func-
> >notify_smc_display_config_after_ps_adjustment(hwmgr);
> 
>  	return 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index f0d0d1f..7ae26f5 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -852,10 +852,6 @@ int polaris_set_asic_special_caps(struct pp_hwmgr
> *hwmgr)
>  	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> 
> 	PHM_PlatformCaps_AutomaticDCTransition);
> 
> -	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> -
> 	PHM_PlatformCaps_TablelessHardwareInterface);
> -
> -
>  	if (hwmgr->chip_id != CHIP_POLARIS10)
>  		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> 
> 	PHM_PlatformCaps_SPLLShutdownSupport);
> @@ -882,9 +878,6 @@ int fiji_set_asic_special_caps(struct pp_hwmgr
> *hwmgr)
>  	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>  			PHM_PlatformCaps_TCPRamping);
> 
> -	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> -			PHM_PlatformCaps_TablelessHardwareInterface);
> -
>  	return 0;
>  }
> 
> @@ -904,9 +897,6 @@ int tonga_set_asic_special_caps(struct pp_hwmgr
> *hwmgr)
>  	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>  		      PHM_PlatformCaps_VCEPowerGating);
> 
> -	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> -			 PHM_PlatformCaps_TablelessHardwareInterface);
> -
>  	return 0;
>  }
> 
> @@ -921,8 +911,6 @@ int topaz_set_asic_special_caps(struct pp_hwmgr
> *hwmgr)
>  	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>  			PHM_PlatformCaps_TCPRamping);
>  	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> -			 PHM_PlatformCaps_TablelessHardwareInterface);
> -	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>  		    PHM_PlatformCaps_EVV);
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index da74f95..594b978 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -435,9 +435,6 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr
> *hwmgr)
> 
>  	hwmgr->backend = data;
> 
> -	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> -			PHM_PlatformCaps_TablelessHardwareInterface);
> -
>  	result = rv_initialize_dpm_defaults(hwmgr);
>  	if (result != 0) {
>  		pr_err("rv_initialize_dpm_defaults failed\n");
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index e5f530b..b7a789f 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -200,9 +200,6 @@ static int vega10_set_features_platform_caps(struct
> pp_hwmgr *hwmgr)
>  				PHM_PlatformCaps_ControlVDDCI);
> 
>  	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> -			PHM_PlatformCaps_TablelessHardwareInterface);
> -
> -	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> 
> 	PHM_PlatformCaps_EnableSMU7ThermalManagement);
> 
>  	sys_info.size = sizeof(struct cgs_system_info);
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 831add4..5c1e6a7 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -109,10 +109,6 @@ enum PHM_BackEnd_Magic {
>  #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE     2
>  #define PHM_PCIE_POWERGATING_TARGET_PHY            3
> 
> -typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
> -				  void *output, void *storage, int result);
> -
> -typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
> 
>  struct phm_set_power_state_input {
>  	const struct pp_hw_power_state *pcurrent_state;
> @@ -149,30 +145,6 @@ struct phm_gfx_arbiter {
>  	uint32_t fclk;
>  };
> 
> -/* Entries in the master tables */
> -struct phm_master_table_item {
> -	phm_check_function isFunctionNeededInRuntimeTable;
> -	phm_table_function tableFunction;
> -};
> -
> -enum phm_master_table_flag {
> -	PHM_MasterTableFlag_None         = 0,
> -	PHM_MasterTableFlag_ExitOnError  = 1,
> -};
> -
> -/* The header of the master tables */
> -struct phm_master_table_header {
> -	uint32_t storage_size;
> -	uint32_t flags;
> -	const struct phm_master_table_item *master_list;
> -};
> -
> -struct phm_runtime_table_header {
> -	uint32_t storage_size;
> -	bool exit_error;
> -	phm_table_function *function_list;
> -};
> -
>  struct phm_clock_array {
>  	uint32_t count;
>  	uint32_t values[1];
> @@ -216,19 +188,6 @@ struct phm_phase_shedding_limits_record {
>  	uint32_t    Mclk;
>  };
> 
> -
> -extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
> -			      struct phm_runtime_table_header *rt_table,
> -			      void *input, void *output);
> -
> -extern int phm_construct_table(struct pp_hwmgr *hwmgr,
> -			       const struct phm_master_table_header
> *master_table,
> -			       struct phm_runtime_table_header *rt_table);
> -
> -extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
> -			     struct phm_runtime_table_header *rt_table);
> -
> -
>  struct phm_uvd_clock_voltage_dependency_record {
>  	uint32_t vclk;
>  	uint32_t dclk;
> @@ -760,13 +719,6 @@ struct pp_hwmgr {
>  	void *backend;
>  	enum PP_DAL_POWERLEVEL dal_power_level;
>  	struct phm_dynamic_state_info dyn_state;
> -	struct phm_runtime_table_header setup_asic;
> -	struct phm_runtime_table_header power_down_asic;
> -	struct phm_runtime_table_header
> disable_dynamic_state_management;
> -	struct phm_runtime_table_header
> enable_dynamic_state_management;
> -	struct phm_runtime_table_header set_power_state;
> -	struct phm_runtime_table_header enable_clock_power_gatings;
> -	struct phm_runtime_table_header display_configuration_changed;
>  	const struct pp_hwmgr_func *hwmgr_func;
>  	const struct pp_table_func *pptable_func;
>  	struct pp_power_state    *ps;
> --
> 1.9.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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