All of lore.kernel.org
 help / color / mirror / Atom feed
From: Pavel Machek <pavel@ucw.cz>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators
Date: Tue, 12 Sep 2017 00:37:12 +0200	[thread overview]
Message-ID: <20170911223712.GA31546@amd> (raw)
In-Reply-To: <37f0d48de4690694c18be3d32483dafee0730859.1504129273.git.shorne@gmail.com>

On Thu 2017-08-31 07:03:11, Stafford Horne wrote:
> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> 
> Simple enough to be compatible with simulation environments,
> such as verilated systems, QEMU and other targets supporting OpenRISC
> SMP.  This also supports our base FPGA SoC's if the cpu frequency is
> upped to 50Mhz.
> 
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> [shorne at gmail.com: Added defconfig]
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
>  arch/openrisc/boot/dts/simple_smp.dts      | 58 ++++++++++++++++++++++++++
>  arch/openrisc/configs/simple_smp_defconfig | 66 ++++++++++++++++++++++++++++++
>  2 files changed, 124 insertions(+)
>  create mode 100644 arch/openrisc/boot/dts/simple_smp.dts
>  create mode 100644 arch/openrisc/configs/simple_smp_defconfig
> 
> diff --git a/arch/openrisc/boot/dts/simple_smp.dts b/arch/openrisc/boot/dts/simple_smp.dts
> new file mode 100644
> index 000000000000..47c54101baae
> --- /dev/null
> +++ b/arch/openrisc/boot/dts/simple_smp.dts
> @@ -0,0 +1,58 @@
> +/dts-v1/;
> +/ {
> +	compatible = "opencores,or1ksim";

You may want to add some comment on top, explaining what this
is... and perhaps link to some page documenting how to set up
qemu/FPGAs?

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 181 bytes
Desc: Digital signature
URL: <http://lists.librecores.org/pipermail/openrisc/attachments/20170912/6e69b8b1/attachment.sig>

WARNING: multiple messages have this Message-ID (diff)
From: Pavel Machek <pavel-+ZI9xUNit7I@public.gmane.org>
To: Stafford Horne <shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: LKML <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	Openrisc
	<openrisc-cunTk1MwBs9a3B2Vnqf2dGD2FQJk+8+b@public.gmane.org>,
	Stefan Kristiansson
	<stefan.kristiansson-MbMCFXIvDHJFcC0YU169RA@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	Jonas Bonn <jonas-A9uVI2HLR7kOP4wsBPIw7w@public.gmane.org>,
	Krzysztof Kozlowski
	<krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators
Date: Tue, 12 Sep 2017 00:37:12 +0200	[thread overview]
Message-ID: <20170911223712.GA31546@amd> (raw)
In-Reply-To: <37f0d48de4690694c18be3d32483dafee0730859.1504129273.git.shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

[-- Attachment #1: Type: text/plain, Size: 1549 bytes --]

On Thu 2017-08-31 07:03:11, Stafford Horne wrote:
> From: Stefan Kristiansson <stefan.kristiansson-MbMCFXIvDHJFcC0YU169RA@public.gmane.org>
> 
> Simple enough to be compatible with simulation environments,
> such as verilated systems, QEMU and other targets supporting OpenRISC
> SMP.  This also supports our base FPGA SoC's if the cpu frequency is
> upped to 50Mhz.
> 
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson-MbMCFXIvDHJFcC0YU169RA@public.gmane.org>
> [shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: Added defconfig]
> Signed-off-by: Stafford Horne <shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  arch/openrisc/boot/dts/simple_smp.dts      | 58 ++++++++++++++++++++++++++
>  arch/openrisc/configs/simple_smp_defconfig | 66 ++++++++++++++++++++++++++++++
>  2 files changed, 124 insertions(+)
>  create mode 100644 arch/openrisc/boot/dts/simple_smp.dts
>  create mode 100644 arch/openrisc/configs/simple_smp_defconfig
> 
> diff --git a/arch/openrisc/boot/dts/simple_smp.dts b/arch/openrisc/boot/dts/simple_smp.dts
> new file mode 100644
> index 000000000000..47c54101baae
> --- /dev/null
> +++ b/arch/openrisc/boot/dts/simple_smp.dts
> @@ -0,0 +1,58 @@
> +/dts-v1/;
> +/ {
> +	compatible = "opencores,or1ksim";

You may want to add some comment on top, explaining what this
is... and perhaps link to some page documenting how to set up
qemu/FPGAs?

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]

WARNING: multiple messages have this Message-ID (diff)
From: Pavel Machek <pavel@ucw.cz>
To: Stafford Horne <shorne@gmail.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
	Openrisc <openrisc@lists.librecores.org>,
	Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Jonas Bonn <jonas@southpole.se>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	devicetree@vger.kernel.org
Subject: Re: [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators
Date: Tue, 12 Sep 2017 00:37:12 +0200	[thread overview]
Message-ID: <20170911223712.GA31546@amd> (raw)
In-Reply-To: <37f0d48de4690694c18be3d32483dafee0730859.1504129273.git.shorne@gmail.com>

[-- Attachment #1: Type: text/plain, Size: 1437 bytes --]

On Thu 2017-08-31 07:03:11, Stafford Horne wrote:
> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> 
> Simple enough to be compatible with simulation environments,
> such as verilated systems, QEMU and other targets supporting OpenRISC
> SMP.  This also supports our base FPGA SoC's if the cpu frequency is
> upped to 50Mhz.
> 
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> [shorne@gmail.com: Added defconfig]
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
>  arch/openrisc/boot/dts/simple_smp.dts      | 58 ++++++++++++++++++++++++++
>  arch/openrisc/configs/simple_smp_defconfig | 66 ++++++++++++++++++++++++++++++
>  2 files changed, 124 insertions(+)
>  create mode 100644 arch/openrisc/boot/dts/simple_smp.dts
>  create mode 100644 arch/openrisc/configs/simple_smp_defconfig
> 
> diff --git a/arch/openrisc/boot/dts/simple_smp.dts b/arch/openrisc/boot/dts/simple_smp.dts
> new file mode 100644
> index 000000000000..47c54101baae
> --- /dev/null
> +++ b/arch/openrisc/boot/dts/simple_smp.dts
> @@ -0,0 +1,58 @@
> +/dts-v1/;
> +/ {
> +	compatible = "opencores,or1ksim";

You may want to add some comment on top, explaining what this
is... and perhaps link to some page documenting how to set up
qemu/FPGAs?

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]

  parent reply	other threads:[~2017-09-11 22:37 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-30 21:58 [OpenRISC] [PATCH 00/13] OpenRISC SMP Support Stafford Horne
2017-08-30 21:58 ` Stafford Horne
2017-08-30 21:58 ` [OpenRISC] [PATCH 01/13] openrisc: use shadow registers to save regs on exception Stafford Horne
2017-08-30 21:58   ` Stafford Horne
2017-09-01  8:02   ` [OpenRISC] " Geert Uytterhoeven
2017-09-01  8:02     ` Geert Uytterhoeven
2017-09-01  8:03     ` Geert Uytterhoeven
2017-09-01  8:03       ` Geert Uytterhoeven
2017-09-01  8:26       ` Stafford Horne
2017-09-01  8:26         ` Stafford Horne
2017-08-30 21:58 ` [OpenRISC] [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true Stafford Horne
2017-08-30 21:58   ` Stafford Horne
2017-09-01  8:06   ` [OpenRISC] " Geert Uytterhoeven
2017-09-01  8:06     ` Geert Uytterhoeven
2017-09-01  8:28     ` Stafford Horne
2017-09-01  8:28       ` Stafford Horne
2017-08-30 21:58 ` [OpenRISC] [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne
2017-08-30 21:58   ` Stafford Horne
2017-08-31  7:46   ` [OpenRISC] " Peter Zijlstra
2017-08-31  7:46     ` Peter Zijlstra
2017-08-31  9:01     ` [OpenRISC] " Stafford Horne
2017-08-31  9:01       ` Stafford Horne
2017-08-30 21:58 ` [OpenRISC] [PATCH 04/13] openrisc: use qspinlocks and qrwlocks Stafford Horne
2017-08-30 21:58   ` Stafford Horne
2017-08-30 21:58 ` [OpenRISC] [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne
2017-08-30 21:58   ` Stafford Horne
2017-08-30 21:58   ` Stafford Horne
2017-08-31  9:28   ` [OpenRISC] " Marc Zyngier
2017-08-31  9:28     ` Marc Zyngier
2017-08-31  9:28     ` Marc Zyngier
2017-09-01  1:24     ` [OpenRISC] " Stafford Horne
2017-09-01  1:24       ` Stafford Horne
2017-09-01  1:24       ` Stafford Horne
2017-09-01 17:25       ` [OpenRISC] " Marc Zyngier
2017-09-01 17:25         ` Marc Zyngier
2017-09-03 22:12         ` [OpenRISC] " Stafford Horne
2017-09-03 22:12           ` Stafford Horne
2017-09-03 22:12           ` Stafford Horne
2017-09-04  7:35           ` [OpenRISC] " Marc Zyngier
2017-09-04  7:35             ` Marc Zyngier
2017-09-04  7:35             ` Marc Zyngier
2017-08-31 10:59   ` [OpenRISC] " Mark Rutland
2017-08-31 10:59     ` Mark Rutland
2017-08-31 10:59     ` Mark Rutland
2017-09-01 13:59     ` [OpenRISC] " Stafford Horne
2017-09-01 13:59       ` Stafford Horne
2017-08-30 21:58 ` [OpenRISC] [PATCH 06/13] openrisc: initial SMP support Stafford Horne
2017-08-30 21:58   ` Stafford Horne
2017-08-30 22:02 ` [OpenRISC] [PATCH 07/13] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne
2017-08-30 22:02   ` Stafford Horne
2017-08-30 22:02 ` [OpenRISC] [PATCH 08/13] openrisc: sleep instead of spin on secondary wait Stafford Horne
2017-08-30 22:02   ` Stafford Horne
2017-08-30 22:02 ` [OpenRISC] [PATCH 09/13] openrisc: add cacheflush support to fix icache aliasing Stafford Horne
2017-08-30 22:02   ` Stafford Horne
2017-08-30 22:03 ` [OpenRISC] [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne
2017-08-30 22:03   ` Stafford Horne
2017-08-30 22:03   ` [OpenRISC] [PATCH 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT Stafford Horne
2017-08-30 22:03     ` Stafford Horne
2017-08-30 22:03   ` [OpenRISC] [PATCH 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne
2017-08-30 22:03     ` Stafford Horne
2017-08-30 22:03   ` [OpenRISC] [PATCH 13/13] openrisc: add tick timer multicore sync logic Stafford Horne
2017-08-30 22:03     ` Stafford Horne
2017-08-31 10:41   ` [OpenRISC] [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators Mark Rutland
2017-08-31 10:41     ` Mark Rutland
2017-08-31 10:41     ` Mark Rutland
2017-08-31 13:05     ` [OpenRISC] " Stafford Horne
2017-08-31 13:05       ` Stafford Horne
2017-09-11 22:37   ` Pavel Machek [this message]
2017-09-11 22:37     ` Pavel Machek
2017-09-11 22:37     ` Pavel Machek
2017-09-11 22:55     ` [OpenRISC] " Stafford Horne
2017-09-11 22:55       ` Stafford Horne
2017-09-11 22:55       ` Stafford Horne
2017-09-12  7:47       ` [OpenRISC] " Pavel Machek
2017-09-12  7:47         ` Pavel Machek
2017-09-12  7:47         ` Pavel Machek
2017-09-12 22:15         ` [OpenRISC] " Stafford Horne
2017-09-12 22:15           ` Stafford Horne

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20170911223712.GA31546@amd \
    --to=pavel@ucw.cz \
    --cc=openrisc@lists.librecores.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.