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* [PATCH 1/3] amdgpu/pp: use array_size to size the pwrvirus tables.
@ 2017-09-29  2:37 Dave Airlie
       [not found] ` <20170929023759.27720-1-airlied-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  0 siblings, 1 reply; 3+ messages in thread
From: Dave Airlie @ 2017-09-29  2:37 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

From: Dave Airlie <airlied@redhat.com>

This avoids fragile hardcoding of array size.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h       | 3 +--
 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h  | 5 +----
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c      | 2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 2 +-
 4 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
index 243de29..e202e56 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
@@ -35,8 +35,7 @@ struct PWR_Command_Table
 };
 typedef struct PWR_Command_Table PWR_Command_Table;
 
-#define PWR_VIRUS_TABLE_SIZE  10243
-static const PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] =
+static const PWR_Command_Table PwrVirusTable[] =
 {
     { 0x100100b6, mmPCIE_INDEX                               },
     { 0x00000000, mmPCIE_DATA                                },
diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
index 7603986..8edd3e7 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
@@ -36,10 +36,7 @@ struct PWR_Command_Table {
 
 typedef struct PWR_Command_Table PWR_Command_Table;
 
-
-#define PWR_VIRUS_TABLE_SIZE  10031
-
-static const PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = {
+static const PWR_Command_Table pwr_virus_table[] = {
 	{ 0x00000000, mmRLC_CNTL                                 },
 	{ 0x00000002, mmRLC_SRM_CNTL                             },
 	{ 0x15000000, mmCP_ME_CNTL                               },
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 3820fe8..289006b 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -167,7 +167,7 @@ static int fiji_setup_pwr_virus(struct pp_hwmgr *hwmgr)
 
 	const PWR_Command_Table *pvirus = PwrVirusTable;
 
-	for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
+	for (i = 0; i < ARRAY_SIZE(PwrVirusTable); i++) {
 		reg  = pvirus->reg;
 		data = pvirus->data;
 		if (reg != 0xffffffff)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index b73b2b4..f039320 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -68,7 +68,7 @@ static int polaris10_setup_pwr_virus(struct pp_hwmgr *hwmgr)
 
 	const PWR_Command_Table *pvirus = pwr_virus_table;
 
-	for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
+	for (i = 0; i < ARRAY_SIZE(pwr_virus_table); i++) {
 		reg  = pvirus->reg;
 		data = pvirus->data;
 		if (reg != 0xffffffff) {
-- 
2.9.4

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^ permalink raw reply related	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2017-09-29  2:37 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-09-29  2:37 [PATCH 1/3] amdgpu/pp: use array_size to size the pwrvirus tables Dave Airlie
     [not found] ` <20170929023759.27720-1-airlied-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-09-29  2:37   ` [PATCH 2/3] amdgpu/pp: rewrite polaris pwrvirus upload code Dave Airlie
2017-09-29  2:37   ` [PATCH 3/3] amdgpu/pp: rewrite fiji pwr virus " Dave Airlie

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