From: Antony Pavlov <antonynpavlov@gmail.com>
To: Oleksij Rempel <linux@rempel-privat.de>
Cc: barebox@lists.infradead.org
Subject: Re: [RFC v4 04/10] RISC-V: add nmon nano-monitor
Date: Sat, 30 Sep 2017 15:22:48 +0300 [thread overview]
Message-ID: <20170930152248.e776e9dcc0fb96b7cc26e854@gmail.com> (raw)
In-Reply-To: <1af67755-749c-41b0-1c53-64a070771b81@rempel-privat.de>
On Fri, 29 Sep 2017 14:26:34 +0200
Oleksij Rempel <linux@rempel-privat.de> wrote:
> Same as for MIPS
>
Yes, I have based arch/riscv on arch/mips.
> Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
...
> > diff --git a/arch/riscv/include/asm/riscv_nmon.h b/arch/riscv/include/asm/riscv_nmon.h
> > new file mode 100644
> > index 000000000..717f61334
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/riscv_nmon.h
>
> may be arch/riscv/include/asm/pbl_nmon.h instead?
> to use same naming shema as for existing arch:
> arch/mips/include/asm/pbl_nmon.h
Contrariwise! I have a plan to sync mips naming schema with riscv.
> every thing else seems to be nearly identical with MIPS, except some
> instruction differences.
Little wonder, since RISC-V ISA looks like reduced MIPS ISA.
I can recomend the notable paper on ISA ideas behind RISC-V
Design of the RISC-V Instruction Set Architecture by Andrew Waterman
http://escholarship.org/uc/item/7zj0b3m7#page-14
> > @@ -0,0 +1,234 @@
> > +/*
> > + * nano-monitor for RISC-V CPU
> > + *
> > + * Copyright (C) 2016, 2017 Antony Pavlov <antonynpavlov@gmail.com>
> > + *
> > + * This file is part of barebox.
> > + * See file CREDITS for list of people who contributed to this project.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2
> > + * as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + */
> > +
> > +#ifndef __ASM_RISCV_NMON_H
> > +#define __ASM_RISCV_NMON_H
> > +
> > +#define CODE_ESC 0x1b
> > +
> > +.macro nmon_outs msg
> > +
> > + la a1, \msg
> > +
> > + jal _nmon_outs
> > +
> > +.endm
> > +
> > +/*
> > + * output a 32-bit value in hex
> > + */
> > +.macro debug_ll_outhexw
> > +#ifdef CONFIG_DEBUG_LL
> > + move t6, a0
> > + li t5, 32
> > +
> > +202:
> > + addi t5, t5, -4
> > + srl a0, t6, t5
> > +
> > + /* output one hex digit */
> > + andi a0, a0, 15
> > + li t4, 10
> > + blt a0, t4, 203f
> > +
> > + addi a0, a0, ('a' - '9' - 1)
> > +
> > +203:
> > + addi a0, a0, '0'
> > +
> > + debug_ll_outc_a0
> > +
> > + li t4, 1
> > + bge t5, t4, 202b
> > +
> > +#endif /* CONFIG_DEBUG_LL */
> > +.endm
> > +
> > +.macro riscv_nmon
> > +
> > +nmon_main_help:
> > +#ifdef CONFIG_NMON_HELP
> > + nmon_outs msg_nmon_help
> > +#endif /* CONFIG_NMON_HELP */
> > +
> > +nmon_main:
> > + nmon_outs msg_prompt
> > +
> > + debug_ll_getc
> > +
> > + li a0, 'q'
> > + bne s0, a0, 3f
> > +
> > + jal _nmon_outc_a0
> > +
> > + j nmon_exit
> > +
> > +3:
> > + li a0, 'd'
> > + beq s0, a0, nmon_cmd_d
> > +
> > + li a0, 'w'
> > + beq s0, a0, nmon_cmd_w
> > +
> > + li a0, 'g'
> > + beq s0, a0, nmon_cmd_g
> > +
> > + j nmon_main_help
> > +
> > +nmon_cmd_d:
> > + jal _nmon_outc_a0
> > +
> > + li a0, ' '
> > + jal _nmon_outc_a0
> > +
> > + jal _nmon_gethexw
> > +
> > + nmon_outs msg_nl
> > +
> > + lw a0, (s0)
> > + debug_ll_outhexw
> > +
> > + j nmon_main
> > +
> > +nmon_cmd_w:
> > + jal _nmon_outc_a0
> > +
> > + li a0, ' '
> > + jal _nmon_outc_a0
> > +
> > + jal _nmon_gethexw
> > + move s2, s0
> > +
> > + li a0, ' '
> > + jal _nmon_outc_a0
> > + jal _nmon_gethexw
> > +
> > + sw s0, 0(s2)
> > + j nmon_main
> > +
> > +nmon_cmd_g:
> > + jal _nmon_outc_a0
> > +
> > + li a0, ' '
> > + jal _nmon_outc_a0
> > +
> > + jal _nmon_gethexw
> > + move s2, s0
> > +
> > + nmon_outs msg_nl
> > +
> > + jalr s2
> > + j nmon_main
> > +
> > +_nmon_outc_a0:
> > + debug_ll_outc_a0
> > + jr ra
> > +
> > +_nmon_outs:
> > +
> > + lb a0, 0(a1)
> > + addi a1, a1, 1
> > + beqz a0, _nmon_jr_ra_exit
> > +
> > + debug_ll_outc_a0
> > +
> > + j _nmon_outs
> > +
> > +_nmon_gethexw:
> > +
> > + li t3, 8
> > + li t2, 0
> > +
> > +_get_hex_digit:
> > + debug_ll_getc
> > +
> > + li s1, CODE_ESC
> > + beq s0, s1, nmon_main
> > +
> > + li s1, '0'
> > + bge s0, s1, 0f
> > + j _get_hex_digit
> > +
> > +0:
> > + li s1, '9'
> > + ble s0, s1, 9f
> > +
> > + li s1, 'f'
> > + ble s0, s1, 1f
> > + j _get_hex_digit
> > +
> > +1:
> > + li s1, 'a'
> > + bge s0, s1, 8f
> > +
> > + j _get_hex_digit
> > +
> > +8: /* s0 \in {'a', 'b' ... 'f'} */
> > + sub a3, s0, s1
> > + addi a3, a3, 0xa
> > + j 0f
> > +
> > +9: /* s0 \in {'0', '1' ... '9'} */
> > + li a3, '0'
> > + sub a3, s0, a3
> > +
> > +0: move a0, s0
> > + debug_ll_outc_a0
> > +
> > + sll t2, t2, 4
> > + or t2, t2, a3
> > + li t0, 1
> > + sub t3, t3, t0
> > +
> > + beqz t3, 0f
> > +
> > + j _get_hex_digit
> > +
> > +0:
> > + move s0, t2
> > +
> > +_nmon_jr_ra_exit:
> > + jr ra
> > +
> > +msg_prompt:
> > + .asciz "\r\nnmon> "
> > +
> > +msg_nl:
> > + .asciz "\r\n"
> > +
> > +msg_bsp:
> > + .asciz "\b \b"
> > +
> > +#ifdef CONFIG_NMON_HELP
> > +msg_nmon_help:
> > + .ascii "\r\n\r\nnmon commands:\r\n"
> > + .ascii " q - quit\r\n"
> > + .ascii " d <addr> - read 32-bit word from <addr>\r\n"
> > + .ascii " w <addr> <val> - write 32-bit word to <addr>\r\n"
> > + .ascii " g <addr> - jump to <addr>\r\n"
> > + .asciz " use <ESC> key to interrupt current command\r\n"
> > +#endif /* CONFIG_NMON_HELP */
> > +
> > + .align 2
> > +nmon_exit:
> > + nmon_outs msg_nl
> > +
> > +.endm
> > +
> > +#endif /* __ASM_RISCV_NMON_H */
> >
>
>
> --
> Regards,
> Oleksij
>
--
Best regards,
Antony Pavlov
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next prev parent reply other threads:[~2017-09-30 12:11 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-28 23:12 [RFC v4 00/10] add initial RISC-V architecture support Antony Pavlov
2017-09-28 23:12 ` [RFC v4 01/10] Add " Antony Pavlov
2017-09-29 12:07 ` Oleksij Rempel
2017-09-30 11:57 ` Antony Pavlov
2017-10-02 7:43 ` Oleksij Rempel
2017-10-02 14:08 ` Antony Pavlov
2017-10-02 10:04 ` Daniel Schultz
2017-10-02 22:15 ` Antony Pavlov
2017-10-02 10:08 ` Daniel Schultz
2017-10-02 22:21 ` Antony Pavlov
2017-10-05 10:55 ` Daniel Schultz
2017-10-06 15:39 ` Antony Pavlov
2017-09-28 23:12 ` [RFC v4 02/10] RISC-V: add Erizo SoC support Antony Pavlov
2017-09-29 12:18 ` Oleksij Rempel
2017-09-30 12:05 ` Antony Pavlov
2017-09-28 23:12 ` [RFC v4 03/10] RISC-V: add low-level debug macros for ns16550 Antony Pavlov
2017-09-28 23:12 ` [RFC v4 04/10] RISC-V: add nmon nano-monitor Antony Pavlov
2017-09-29 12:26 ` Oleksij Rempel
2017-09-30 12:22 ` Antony Pavlov [this message]
2017-09-28 23:12 ` [RFC v4 05/10] RISC-V: erizo: add DEBUG_LL support Antony Pavlov
2017-09-28 23:12 ` [RFC v4 06/10] RISC-V: erizo: enable NMON Antony Pavlov
2017-09-28 23:12 ` [RFC v4 07/10] RISC-V: erizo: add nmon image creation Antony Pavlov
2017-09-28 23:12 ` [RFC v4 08/10] RISC-V: add erizo_generic_defconfig Antony Pavlov
2017-09-29 12:29 ` Oleksij Rempel
2017-09-30 12:38 ` Antony Pavlov
2017-09-28 23:12 ` [RFC v4 09/10] scripts: add nmon-loader Antony Pavlov
2017-09-28 23:12 ` [RFC v4 10/10] Documentation: add RISC-V docs Antony Pavlov
2017-09-29 12:35 ` Oleksij Rempel
2017-09-30 12:34 ` Antony Pavlov
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