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* [PATCH 1/5] memorder: Add missed comma
@ 2017-10-17  2:20 SeongJae Park
  2017-10-17  2:20 ` [PATCH 2/5] memorder: Close unclosed parenthesis SeongJae Park
                   ` (3 more replies)
  0 siblings, 4 replies; 6+ messages in thread
From: SeongJae Park @ 2017-10-17  2:20 UTC (permalink / raw)
  To: paulmck; +Cc: perfbook, SeongJae Park

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index 8a3da54..e911e79 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -4064,7 +4064,7 @@ in Alpha's heyday.
 One could place an \co{smp_rmb()} primitive
 between the pointer fetch and dereference in order to force Alpha
 to order the pointer fetch with the later dependent load.
-However, this imposes unneeded overhead on systems (such as ARM
+However, this imposes unneeded overhead on systems (such as ARM,
 Itanium, PPC, and SPARC) that respect data dependencies on the read side.
 A \co{smp_read_barrier_depends()} primitive has therefore been added to the
 Linux kernel to eliminate overhead on these systems.
-- 
2.10.0


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 2/5] memorder: Close unclosed parenthesis
  2017-10-17  2:20 [PATCH 1/5] memorder: Add missed comma SeongJae Park
@ 2017-10-17  2:20 ` SeongJae Park
  2017-10-17  2:20 ` [PATCH 3/5] memorder: Add missed unbreakable space before line number SeongJae Park
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 6+ messages in thread
From: SeongJae Park @ 2017-10-17  2:20 UTC (permalink / raw)
  To: paulmck; +Cc: perfbook, SeongJae Park

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index e911e79..cc1497b 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -4172,7 +4172,7 @@ For more on Alpha, see its reference manual~\cite{ALPHA2002}.
 The ARM family of CPUs is extremely popular in embedded applications,
 particularly for power-constrained applications such as cellphones.
 Its memory model is similar to that of \Power{}
-(see Section~\ref{sec:memorder:POWER / PowerPC}, but ARM uses a
+(see Section~\ref{sec:memorder:POWER / PowerPC}), but ARM uses a
 different set of memory-barrier instructions~\cite{ARMv7A:2010}:

 \begin{description}
-- 
2.10.0


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 3/5] memorder: Add missed unbreakable space before line number
  2017-10-17  2:20 [PATCH 1/5] memorder: Add missed comma SeongJae Park
  2017-10-17  2:20 ` [PATCH 2/5] memorder: Close unclosed parenthesis SeongJae Park
@ 2017-10-17  2:20 ` SeongJae Park
  2017-10-17  2:20 ` [PATCH 4/5] memorder: Fix typo on instruction name (LDAR -> LDLAR) SeongJae Park
  2017-10-17  2:20 ` [PATCH 5/5] memorder: Use zSeries name consistently SeongJae Park
  3 siblings, 0 replies; 6+ messages in thread
From: SeongJae Park @ 2017-10-17  2:20 UTC (permalink / raw)
  To: paulmck; +Cc: perfbook, SeongJae Park

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index cc1497b..11fa280 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -4240,7 +4240,7 @@ On the other hand, the combination of the conditional branch on line~2
 and the \co{ISB} instruction on line~6 ensures that
 the load on line~7 happens after the load on line~1.
 Note that inserting an additional \co{ISB} instruction somewhere between
-lines~3 and 4 would enforce ordering between lines~1 and 5.
+lines~3 and~4 would enforce ordering between lines~1 and~5.

 \subsection{ARMv8}

-- 
2.10.0


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 4/5] memorder: Fix typo on instruction name (LDAR -> LDLAR)
  2017-10-17  2:20 [PATCH 1/5] memorder: Add missed comma SeongJae Park
  2017-10-17  2:20 ` [PATCH 2/5] memorder: Close unclosed parenthesis SeongJae Park
  2017-10-17  2:20 ` [PATCH 3/5] memorder: Add missed unbreakable space before line number SeongJae Park
@ 2017-10-17  2:20 ` SeongJae Park
  2017-10-17  2:20 ` [PATCH 5/5] memorder: Use zSeries name consistently SeongJae Park
  3 siblings, 0 replies; 6+ messages in thread
From: SeongJae Park @ 2017-10-17  2:20 UTC (permalink / raw)
  To: paulmck; +Cc: perfbook, SeongJae Park

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index 11fa280..28faeec 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -4260,7 +4260,7 @@ and store-release (\co{STLLRB}, \co{STLLRH}, and \co{STLLR})
 instructions.
 These instructions act as ``half memory barriers'', so that
 ARMv8 CPUs can reorder previous accesses with a later \co{LDLAR}
-instruction, but are prohibited from reordering an earlier \co{LDAR}
+instruction, but are prohibited from reordering an earlier \co{LDLAR}
 instruction with later accesses, as fancifully depicted in
 Figure~\ref{fig:memorder:Half Memory Barrier}.
 Similarly, ARMv8 CPUs can reorder an earlier \co{STLLR} instruction with
-- 
2.10.0


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 5/5] memorder: Use zSeries name consistently
  2017-10-17  2:20 [PATCH 1/5] memorder: Add missed comma SeongJae Park
                   ` (2 preceding siblings ...)
  2017-10-17  2:20 ` [PATCH 4/5] memorder: Fix typo on instruction name (LDAR -> LDLAR) SeongJae Park
@ 2017-10-17  2:20 ` SeongJae Park
  2017-10-17 16:16   ` Paul E. McKenney
  3 siblings, 1 reply; 6+ messages in thread
From: SeongJae Park @ 2017-10-17  2:20 UTC (permalink / raw)
  To: paulmck; +Cc: perfbook, SeongJae Park

Table for `Summary of Memory Ordering` is using term `z Systems` while a
subsection about its description calls it `zSeries`.  Because the
subsection is referencing the table, it would be confuse.  This commit
modifies the table to use `zSeries` term consistently.

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index 28faeec..df4d74c 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -3753,11 +3753,11 @@ dependencies.
 		\rotatebox{90}{x86}
 	  \end{picture}
 	& \begin{picture}(6,60)(0,0)
-		\rotatebox{90}{z~Systems}
+		\rotatebox{90}{z~Series}
 	  \end{picture}
 	\\
 	\cmidrule(r){1-2} \cmidrule{3-13}
-%		 Alpha ARMv8 ARMv7 Itanium MIPS PA-RISC -CPUs PPC SPARC x86 z Systems
+%		 Alpha ARMv8 ARMv7 Itanium MIPS PA-RISC -CPUs PPC SPARC x86 z Series
 \cellcolor{white}
 	Memory Ordering
 	& Loads Reordered After Loads or Stores?
-- 
2.10.0


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH 5/5] memorder: Use zSeries name consistently
  2017-10-17  2:20 ` [PATCH 5/5] memorder: Use zSeries name consistently SeongJae Park
@ 2017-10-17 16:16   ` Paul E. McKenney
  0 siblings, 0 replies; 6+ messages in thread
From: Paul E. McKenney @ 2017-10-17 16:16 UTC (permalink / raw)
  To: SeongJae Park; +Cc: perfbook

On Tue, Oct 17, 2017 at 11:20:54AM +0900, SeongJae Park wrote:
> Table for `Summary of Memory Ordering` is using term `z Systems` while a
> subsection about its description calls it `zSeries`.  Because the
> subsection is referencing the table, it would be confuse.  This commit
> modifies the table to use `zSeries` term consistently.
> 
> Signed-off-by: SeongJae Park <sj38.park@gmail.com>

I applied the first four, good eyes, thank you!

This one was a problem, and I fixed it only two days ago by changing
the section heading to "z Systems", which is the new name.  So good
catch on the inconsistency, but "z Systems" is the new name.

							Thanx, Paul

> ---
>  memorder/memorder.tex | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/memorder/memorder.tex b/memorder/memorder.tex
> index 28faeec..df4d74c 100644
> --- a/memorder/memorder.tex
> +++ b/memorder/memorder.tex
> @@ -3753,11 +3753,11 @@ dependencies.
>  		\rotatebox{90}{x86}
>  	  \end{picture}
>  	& \begin{picture}(6,60)(0,0)
> -		\rotatebox{90}{z~Systems}
> +		\rotatebox{90}{z~Series}
>  	  \end{picture}
>  	\\
>  	\cmidrule(r){1-2} \cmidrule{3-13}
> -%		 Alpha ARMv8 ARMv7 Itanium MIPS PA-RISC -CPUs PPC SPARC x86 z Systems
> +%		 Alpha ARMv8 ARMv7 Itanium MIPS PA-RISC -CPUs PPC SPARC x86 z Series
>  \cellcolor{white}
>  	Memory Ordering
>  	& Loads Reordered After Loads or Stores?
> -- 
> 2.10.0
> 


^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2017-10-17 16:16 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-10-17  2:20 [PATCH 1/5] memorder: Add missed comma SeongJae Park
2017-10-17  2:20 ` [PATCH 2/5] memorder: Close unclosed parenthesis SeongJae Park
2017-10-17  2:20 ` [PATCH 3/5] memorder: Add missed unbreakable space before line number SeongJae Park
2017-10-17  2:20 ` [PATCH 4/5] memorder: Fix typo on instruction name (LDAR -> LDLAR) SeongJae Park
2017-10-17  2:20 ` [PATCH 5/5] memorder: Use zSeries name consistently SeongJae Park
2017-10-17 16:16   ` Paul E. McKenney

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