From: Christoffer Dall <cdall@linaro.org>
To: Mark Rutland <mark.rutland@arm.com>
Cc: kvm@vger.kernel.org, Marc Zyngier <marc.zyngier@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu
Subject: Re: [PATCH v2 2/8] arm: KVM: Add optimized PIPT icache flushing
Date: Sat, 21 Oct 2017 17:18:17 +0200 [thread overview]
Message-ID: <20171021151817.GE12618@cbox> (raw)
In-Reply-To: <20171020165440.sdqfdyt6jsmbjcx5@lakrids.cambridge.arm.com>
On Fri, Oct 20, 2017 at 05:54:40PM +0100, Mark Rutland wrote:
> On Fri, Oct 20, 2017 at 05:53:39PM +0100, Marc Zyngier wrote:
> > Hi Mark,
> >
> > On 20/10/17 17:27, Mark Rutland wrote:
> > > Hi Marc,
> > >
> > > On Fri, Oct 20, 2017 at 04:48:58PM +0100, Marc Zyngier wrote:
> > >> @@ -181,18 +185,40 @@ static inline void __invalidate_icache_guest_page(struct kvm_vcpu *vcpu,
> > >> return;
> > >> }
> > >>
> > >> - /* PIPT cache. As for the d-side, use a temporary kernel mapping. */
> > >> + /*
> > >> + * CTR IminLine contains Log2 of the number of words in the
> > >> + * cache line, so we can get the number of words as
> > >> + * 2 << (IminLine - 1). To get the number of bytes, we
> > >> + * multiply by 4 (the number of bytes in a 32-bit word), and
> > >> + * get 4 << (IminLine).
> > >> + */
> > >> + iclsz = 4 << (read_cpuid(CPUID_CACHETYPE) & 0xf);
> > >> +
> > >> while (size) {
> > >> void *va = kmap_atomic_pfn(pfn);
> > >> + void *end = va + PAGE_SIZE;
> > >> + void *addr = va;
> > >>
> > >> - __cpuc_coherent_user_range((unsigned long)va,
> > >> - (unsigned long)va + PAGE_SIZE);
> > >> + do {
> > >> + write_sysreg(addr, ICIMVAU);
> > >> + addr += iclsz;
> > >> + } while (addr < end);
> > >> +
> > >> + dsb(ishst);
> > >
> > > I believe this needs to be ISH rather than ISHST.
> > >
> > > Per, ARM DDI 0487B.b, page G3-4701, "G3.4 AArch32 cache and branch
> > > predictor support":
> > >
> > > A DSB or DMB instruction intended to ensure the completion of cache
> > > maintenance instructions or branch predictor instructions must have
> > > an access type of both loads and stores.
> >
> > Right. This actually comes from 6abdd491698a ("ARM: mm: use
> > inner-shareable barriers for TLB and user cache operations"), and the
> > ARMv7 ARM doesn't mention any of this.
>
> Ah; so it doesn't. :/
>
> > My take is that we want to be consistent. Given that KVM/ARM on 32bit is
> > basically ARMv7 only, I'd rather keep the ST version of the barrier
> > here, and change it everywhere if/when someone decides to support a
> > 32bit kernel on ARMv8 (yes, we already do as a guest, but it doesn't
> > seem to really matter so far).
>
> Keeping things consistent makes sense to me.
>
Does that mea this is an ack/reviewed-by ?
Thanks,
-Christoffer
WARNING: multiple messages have this Message-ID (diff)
From: cdall@linaro.org (Christoffer Dall)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/8] arm: KVM: Add optimized PIPT icache flushing
Date: Sat, 21 Oct 2017 17:18:17 +0200 [thread overview]
Message-ID: <20171021151817.GE12618@cbox> (raw)
In-Reply-To: <20171020165440.sdqfdyt6jsmbjcx5@lakrids.cambridge.arm.com>
On Fri, Oct 20, 2017 at 05:54:40PM +0100, Mark Rutland wrote:
> On Fri, Oct 20, 2017 at 05:53:39PM +0100, Marc Zyngier wrote:
> > Hi Mark,
> >
> > On 20/10/17 17:27, Mark Rutland wrote:
> > > Hi Marc,
> > >
> > > On Fri, Oct 20, 2017 at 04:48:58PM +0100, Marc Zyngier wrote:
> > >> @@ -181,18 +185,40 @@ static inline void __invalidate_icache_guest_page(struct kvm_vcpu *vcpu,
> > >> return;
> > >> }
> > >>
> > >> - /* PIPT cache. As for the d-side, use a temporary kernel mapping. */
> > >> + /*
> > >> + * CTR IminLine contains Log2 of the number of words in the
> > >> + * cache line, so we can get the number of words as
> > >> + * 2 << (IminLine - 1). To get the number of bytes, we
> > >> + * multiply by 4 (the number of bytes in a 32-bit word), and
> > >> + * get 4 << (IminLine).
> > >> + */
> > >> + iclsz = 4 << (read_cpuid(CPUID_CACHETYPE) & 0xf);
> > >> +
> > >> while (size) {
> > >> void *va = kmap_atomic_pfn(pfn);
> > >> + void *end = va + PAGE_SIZE;
> > >> + void *addr = va;
> > >>
> > >> - __cpuc_coherent_user_range((unsigned long)va,
> > >> - (unsigned long)va + PAGE_SIZE);
> > >> + do {
> > >> + write_sysreg(addr, ICIMVAU);
> > >> + addr += iclsz;
> > >> + } while (addr < end);
> > >> +
> > >> + dsb(ishst);
> > >
> > > I believe this needs to be ISH rather than ISHST.
> > >
> > > Per, ARM DDI 0487B.b, page G3-4701, "G3.4 AArch32 cache and branch
> > > predictor support":
> > >
> > > A DSB or DMB instruction intended to ensure the completion of cache
> > > maintenance instructions or branch predictor instructions must have
> > > an access type of both loads and stores.
> >
> > Right. This actually comes from 6abdd491698a ("ARM: mm: use
> > inner-shareable barriers for TLB and user cache operations"), and the
> > ARMv7 ARM doesn't mention any of this.
>
> Ah; so it doesn't. :/
>
> > My take is that we want to be consistent. Given that KVM/ARM on 32bit is
> > basically ARMv7 only, I'd rather keep the ST version of the barrier
> > here, and change it everywhere if/when someone decides to support a
> > 32bit kernel on ARMv8 (yes, we already do as a guest, but it doesn't
> > seem to really matter so far).
>
> Keeping things consistent makes sense to me.
>
Does that mea this is an ack/reviewed-by ?
Thanks,
-Christoffer
next prev parent reply other threads:[~2017-10-21 15:17 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-20 15:48 [PATCH v2 0/8] arm/arm64: KVM: limit icache invalidation to prefetch aborts Marc Zyngier
2017-10-20 15:48 ` Marc Zyngier
2017-10-20 15:48 ` [PATCH v2 1/8] arm64: KVM: Add invalidate_icache_range helper Marc Zyngier
2017-10-20 15:48 ` Marc Zyngier
2017-10-23 12:05 ` Will Deacon
2017-10-23 12:05 ` Will Deacon
2017-10-23 12:37 ` Marc Zyngier
2017-10-23 12:37 ` Marc Zyngier
2017-10-23 12:37 ` Marc Zyngier
2017-10-23 13:07 ` Will Deacon
2017-10-23 13:07 ` Will Deacon
2017-10-20 15:48 ` [PATCH v2 2/8] arm: KVM: Add optimized PIPT icache flushing Marc Zyngier
2017-10-20 15:48 ` Marc Zyngier
2017-10-20 16:27 ` Mark Rutland
2017-10-20 16:27 ` Mark Rutland
2017-10-20 16:53 ` Marc Zyngier
2017-10-20 16:53 ` Marc Zyngier
2017-10-20 16:54 ` Mark Rutland
2017-10-20 16:54 ` Mark Rutland
2017-10-21 15:18 ` Christoffer Dall [this message]
2017-10-21 15:18 ` Christoffer Dall
2017-10-31 13:51 ` Mark Rutland
2017-10-31 13:51 ` Mark Rutland
2017-10-20 15:48 ` [PATCH v2 3/8] arm64: KVM: PTE/PMD S2 XN bit definition Marc Zyngier
2017-10-20 15:48 ` Marc Zyngier
2017-10-20 15:49 ` [PATCH v2 4/8] KVM: arm/arm64: Limit icache invalidation to prefetch aborts Marc Zyngier
2017-10-20 15:49 ` Marc Zyngier
2017-10-20 15:49 ` [PATCH v2 5/8] KVM: arm/arm64: Only clean the dcache on translation fault Marc Zyngier
2017-10-20 15:49 ` Marc Zyngier
2017-10-20 15:49 ` [PATCH v2 6/8] KVM: arm/arm64: Preserve Exec permission across R/W permission faults Marc Zyngier
2017-10-20 15:49 ` Marc Zyngier
2017-10-21 15:17 ` Christoffer Dall
2017-10-21 15:17 ` Christoffer Dall
2017-10-20 15:49 ` [PATCH v2 7/8] KVM: arm/arm64: Drop vcpu parameter from guest cache maintenance operartions Marc Zyngier
2017-10-20 15:49 ` Marc Zyngier
2017-10-20 15:49 ` [PATCH v2 8/8] KVM: arm/arm64: Detangle kvm_mmu.h from kvm_hyp.h Marc Zyngier
2017-10-20 15:49 ` Marc Zyngier
2017-10-21 15:24 ` [PATCH v2 0/8] arm/arm64: KVM: limit icache invalidation to prefetch aborts Christoffer Dall
2017-10-21 15:24 ` Christoffer Dall
2017-10-22 9:20 ` Marc Zyngier
2017-10-22 9:20 ` Marc Zyngier
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