diff for duplicates of <20171102081205.GG11011@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index 804ac80..f0ad112 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,13 +1,13 @@ -On 10/05, sean.wang@mediatek.com wrote: -> From: Chen Zhong <chen.zhong@mediatek.com> +On 10/05, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote: +> From: Chen Zhong <chen.zhong-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> > > Since the previous setup always sets the PLL using crystal 26MHz, this > doesn't always happen in every MediaTek platform. So the patch added > flexibility for assigning extra member for determining the PLL source > clock. > -> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> -> Signed-off-by: Sean Wang <sean.wang@mediatek.com> +> Signed-off-by: Chen Zhong <chen.zhong-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> +> Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> > --- Applied to clk-next diff --git a/a/content_digest b/N1/content_digest index 83ef3cb..c047236 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,32 +1,33 @@ "ref\0cover.1507174799.git.sean.wang@mediatek.com\0" "ref\0b90d46284cb527d1412352606912f5e8d18b3e53.1507174799.git.sean.wang@mediatek.com\0" - "From\0Stephen Boyd <sboyd@codeaurora.org>\0" + "ref\0b90d46284cb527d1412352606912f5e8d18b3e53.1507174799.git.sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org\0" + "From\0Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\0" "Subject\0Re: [PATCH v2 2/4] clk: mediatek: add the option for determining PLL source clock\0" "Date\0Thu, 2 Nov 2017 01:12:05 -0700\0" - "To\0sean.wang@mediatek.com\0" - "Cc\0mturquette@baylibre.com" - robh+dt@kernel.org - matthias.bgg@gmail.com - mark.rutland@arm.com - p.zabel@pengutronix.de - devicetree@vger.kernel.org - linux-mediatek@lists.infradead.org - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-kernel@vger.kernel.org - " Chen Zhong <chen.zhong@mediatek.com>\0" + "To\0sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org\0" + "Cc\0mark.rutland-5wv7dgnIgG8@public.gmane.org" + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org + matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org + Chen Zhong <chen.zhong-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" - "On 10/05, sean.wang@mediatek.com wrote:\n" - "> From: Chen Zhong <chen.zhong@mediatek.com>\n" + "On 10/05, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote:\n" + "> From: Chen Zhong <chen.zhong-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>\n" "> \n" "> Since the previous setup always sets the PLL using crystal 26MHz, this\n" "> doesn't always happen in every MediaTek platform. So the patch added\n" "> flexibility for assigning extra member for determining the PLL source\n" "> clock.\n" "> \n" - "> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>\n" - "> Signed-off-by: Sean Wang <sean.wang@mediatek.com>\n" + "> Signed-off-by: Chen Zhong <chen.zhong-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>\n" + "> Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>\n" "> ---\n" "\n" "Applied to clk-next\n" @@ -35,4 +36,4 @@ "Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,\n" a Linux Foundation Collaborative Project -5f5135079fb74a452c2024f3fc4ccb053b68e22523ae8b76dd7a8ad5dddea87f +6101b815f9dad0f7ece5b20766ec7d6454b450e151d3ff45ebaca638b3ee72ad
diff --git a/a/1.txt b/N2/1.txt index 804ac80..7b7d7df 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,4 +1,4 @@ -On 10/05, sean.wang@mediatek.com wrote: +On 10/05, sean.wang at mediatek.com wrote: > From: Chen Zhong <chen.zhong@mediatek.com> > > Since the previous setup always sets the PLL using crystal 26MHz, this diff --git a/a/content_digest b/N2/content_digest index 83ef3cb..5ff152b 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,23 +1,12 @@ "ref\0cover.1507174799.git.sean.wang@mediatek.com\0" "ref\0b90d46284cb527d1412352606912f5e8d18b3e53.1507174799.git.sean.wang@mediatek.com\0" - "From\0Stephen Boyd <sboyd@codeaurora.org>\0" - "Subject\0Re: [PATCH v2 2/4] clk: mediatek: add the option for determining PLL source clock\0" + "From\0sboyd@codeaurora.org (Stephen Boyd)\0" + "Subject\0[PATCH v2 2/4] clk: mediatek: add the option for determining PLL source clock\0" "Date\0Thu, 2 Nov 2017 01:12:05 -0700\0" - "To\0sean.wang@mediatek.com\0" - "Cc\0mturquette@baylibre.com" - robh+dt@kernel.org - matthias.bgg@gmail.com - mark.rutland@arm.com - p.zabel@pengutronix.de - devicetree@vger.kernel.org - linux-mediatek@lists.infradead.org - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-kernel@vger.kernel.org - " Chen Zhong <chen.zhong@mediatek.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "On 10/05, sean.wang@mediatek.com wrote:\n" + "On 10/05, sean.wang at mediatek.com wrote:\n" "> From: Chen Zhong <chen.zhong@mediatek.com>\n" "> \n" "> Since the previous setup always sets the PLL using crystal 26MHz, this\n" @@ -35,4 +24,4 @@ "Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,\n" a Linux Foundation Collaborative Project -5f5135079fb74a452c2024f3fc4ccb053b68e22523ae8b76dd7a8ad5dddea87f +38246758bf36e0a9d775ff6c276ad9195c3c2e6ef0b9674c0d5c75a150048854
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.