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From: Stephen Boyd <sboyd@codeaurora.org>
To: sean.wang@mediatek.com
Cc: mturquette@baylibre.com, robh+dt@kernel.org,
	matthias.bgg@gmail.com, mark.rutland@arm.com,
	p.zabel@pengutronix.de, devicetree@vger.kernel.org,
	linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Chen Zhong <chen.zhong@mediatek.com>
Subject: Re: [PATCH v2 2/4] clk: mediatek: add the option for determining PLL source clock
Date: Thu, 2 Nov 2017 01:12:05 -0700	[thread overview]
Message-ID: <20171102081205.GG11011@codeaurora.org> (raw)
In-Reply-To: <b90d46284cb527d1412352606912f5e8d18b3e53.1507174799.git.sean.wang@mediatek.com>

On 10/05, sean.wang@mediatek.com wrote:
> From: Chen Zhong <chen.zhong@mediatek.com>
> 
> Since the previous setup always sets the PLL using crystal 26MHz, this
> doesn't always happen in every MediaTek platform. So the patch added
> flexibility for assigning extra member for determining the PLL source
> clock.
> 
> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org
Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org,
	matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
	Chen Zhong <chen.zhong-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>,
	linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH v2 2/4] clk: mediatek: add the option for determining PLL source clock
Date: Thu, 2 Nov 2017 01:12:05 -0700	[thread overview]
Message-ID: <20171102081205.GG11011@codeaurora.org> (raw)
In-Reply-To: <b90d46284cb527d1412352606912f5e8d18b3e53.1507174799.git.sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>

On 10/05, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote:
> From: Chen Zhong <chen.zhong-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> 
> Since the previous setup always sets the PLL using crystal 26MHz, this
> doesn't always happen in every MediaTek platform. So the patch added
> flexibility for assigning extra member for determining the PLL source
> clock.
> 
> Signed-off-by: Chen Zhong <chen.zhong-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/4] clk: mediatek: add the option for determining PLL source clock
Date: Thu, 2 Nov 2017 01:12:05 -0700	[thread overview]
Message-ID: <20171102081205.GG11011@codeaurora.org> (raw)
In-Reply-To: <b90d46284cb527d1412352606912f5e8d18b3e53.1507174799.git.sean.wang@mediatek.com>

On 10/05, sean.wang at mediatek.com wrote:
> From: Chen Zhong <chen.zhong@mediatek.com>
> 
> Since the previous setup always sets the PLL using crystal 26MHz, this
> doesn't always happen in every MediaTek platform. So the patch added
> flexibility for assigning extra member for determining the PLL source
> clock.
> 
> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

  reply	other threads:[~2017-11-02  8:12 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <cover.1507174799.git.sean.wang@mediatek.com>
2017-10-05  3:50 ` [PATCH v2 1/4] dt-bindings: clock: mediatek: document clk bindings for MediaTek MT7622 SoC sean.wang
2017-10-05  3:50   ` sean.wang at mediatek.com
2017-10-05  3:50   ` sean.wang
2017-11-02  8:12   ` Stephen Boyd
2017-11-02  8:12     ` Stephen Boyd
2017-10-05  3:50 ` [PATCH v2 2/4] clk: mediatek: add the option for determining PLL source clock sean.wang
2017-10-05  3:50   ` sean.wang at mediatek.com
2017-10-05  3:50   ` sean.wang
2017-11-02  8:12   ` Stephen Boyd [this message]
2017-11-02  8:12     ` Stephen Boyd
2017-11-02  8:12     ` Stephen Boyd
2017-10-05  3:50 ` [PATCH v2 3/4] clk: mediatek: add clock support for MT7622 SoC sean.wang
2017-10-05  3:50   ` sean.wang at mediatek.com
2017-10-05  3:50   ` sean.wang
2017-11-02  8:12   ` Stephen Boyd
2017-11-02  8:12     ` Stephen Boyd
2017-11-02  8:12     ` Stephen Boyd
2017-10-05  3:50 ` [PATCH v2 4/4] clk: mediatek: add clocks dt-bindings required header " sean.wang
2017-10-05  3:50   ` sean.wang at mediatek.com
2017-10-05  3:50   ` sean.wang
2017-11-02  8:11   ` Stephen Boyd
2017-11-02  8:11     ` Stephen Boyd

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