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From: mathieu.poirier@linaro.org (Mathieu Poirier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 13/17] coresight etr: Do not clean ETR trace buffer
Date: Thu, 2 Nov 2017 14:36:23 -0600	[thread overview]
Message-ID: <20171102203623.GE23320@xps15> (raw)
In-Reply-To: <20171019171553.24056-14-suzuki.poulose@arm.com>

On Thu, Oct 19, 2017 at 06:15:49PM +0100, Suzuki K Poulose wrote:
> We zero out the entire trace buffer used for ETR before it
> is enabled, for helping with debugging. Since we could be
> restoring a session in perf mode, this could destroy the data.

I'm not sure to follow you with "... restoring a session in perf mode ...". 
When operating from the perf interface all the memory allocated for a session is
cleanup after, there is no re-using of memory as in sysFS.

> Get rid of this step, if someone wants to debug, they can always
> add it as and when needed.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-tmc-etr.c | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index 31353fc34b53..849684f85443 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -971,8 +971,6 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
>  		return;
>  
>  	drvdata->etr_buf = etr_buf;
> -	/* Zero out the memory to help with debug */
> -	memset(etr_buf->vaddr, 0, etr_buf->size);

I agree, this can be costly when dealing with large areas of memory.

>  
>  	CS_UNLOCK(drvdata->base);
>  
> @@ -1267,9 +1265,8 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata)
>  	if (drvdata->mode == CS_MODE_SYSFS) {
>  		/*
>  		 * The trace run will continue with the same allocated trace
> -		 * buffer. The trace buffer is cleared in tmc_etr_enable_hw(),
> -		 * so we don't have to explicitly clear it. Also, since the
> -		 * tracer is still enabled drvdata::buf can't be NULL.
> +		 * buffer. Since the tracer is still enabled drvdata::buf can't
> +		 * be NULL.
>  		 */
>  		tmc_etr_enable_hw(drvdata, drvdata->sysfs_buf);
>  	} else {
> -- 
> 2.13.6
> 

WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, rob.walker@arm.com,
	mike.leach@linaro.org, coresight@lists.linaro.org
Subject: Re: [PATCH 13/17] coresight etr: Do not clean ETR trace buffer
Date: Thu, 2 Nov 2017 14:36:23 -0600	[thread overview]
Message-ID: <20171102203623.GE23320@xps15> (raw)
In-Reply-To: <20171019171553.24056-14-suzuki.poulose@arm.com>

On Thu, Oct 19, 2017 at 06:15:49PM +0100, Suzuki K Poulose wrote:
> We zero out the entire trace buffer used for ETR before it
> is enabled, for helping with debugging. Since we could be
> restoring a session in perf mode, this could destroy the data.

I'm not sure to follow you with "... restoring a session in perf mode ...". 
When operating from the perf interface all the memory allocated for a session is
cleanup after, there is no re-using of memory as in sysFS.

> Get rid of this step, if someone wants to debug, they can always
> add it as and when needed.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-tmc-etr.c | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index 31353fc34b53..849684f85443 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -971,8 +971,6 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
>  		return;
>  
>  	drvdata->etr_buf = etr_buf;
> -	/* Zero out the memory to help with debug */
> -	memset(etr_buf->vaddr, 0, etr_buf->size);

I agree, this can be costly when dealing with large areas of memory.

>  
>  	CS_UNLOCK(drvdata->base);
>  
> @@ -1267,9 +1265,8 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata)
>  	if (drvdata->mode == CS_MODE_SYSFS) {
>  		/*
>  		 * The trace run will continue with the same allocated trace
> -		 * buffer. The trace buffer is cleared in tmc_etr_enable_hw(),
> -		 * so we don't have to explicitly clear it. Also, since the
> -		 * tracer is still enabled drvdata::buf can't be NULL.
> +		 * buffer. Since the tracer is still enabled drvdata::buf can't
> +		 * be NULL.
>  		 */
>  		tmc_etr_enable_hw(drvdata, drvdata->sysfs_buf);
>  	} else {
> -- 
> 2.13.6
> 

  reply	other threads:[~2017-11-02 20:36 UTC|newest]

Thread overview: 112+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-19 17:15 [PATCH 00/17] coresight: perf: TMC ETR backend support Suzuki K Poulose
2017-10-19 17:15 ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 01/17] coresight etr: Disallow perf mode temporarily Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 02/17] coresight tmc: Hide trace buffer handling for file read Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-10-20 12:34   ` Julien Thierry
2017-10-20 12:34     ` Julien Thierry
2017-11-01  9:55     ` Suzuki K Poulose
2017-11-01  9:55       ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 03/17] coresight: Add helper for inserting synchronization packets Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-10-30 21:44   ` Mathieu Poirier
2017-10-30 21:44     ` Mathieu Poirier
2017-11-01 10:01     ` Suzuki K Poulose
2017-11-01 10:01       ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 04/17] coresight: Add generic TMC sg table framework Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-10-31 22:13   ` Mathieu Poirier
2017-10-31 22:13     ` Mathieu Poirier
2017-11-01 10:09     ` Suzuki K Poulose
2017-11-01 10:09       ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 05/17] coresight: Add support for TMC ETR SG unit Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-10-20 16:25   ` Julien Thierry
2017-10-20 16:25     ` Julien Thierry
2017-11-01 10:11     ` Suzuki K Poulose
2017-11-01 10:11       ` Suzuki K Poulose
2017-11-01 20:41   ` Mathieu Poirier
2017-11-01 20:41     ` Mathieu Poirier
2017-10-19 17:15 ` [PATCH 06/17] coresight: tmc: Make ETR SG table circular Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-10-20 17:11   ` Julien Thierry
2017-10-20 17:11     ` Julien Thierry
2017-11-01 10:12     ` Suzuki K Poulose
2017-11-01 10:12       ` Suzuki K Poulose
2017-11-01 23:47   ` Mathieu Poirier
2017-11-01 23:47     ` Mathieu Poirier
2017-11-02 12:00     ` Suzuki K Poulose
2017-11-02 12:00       ` Suzuki K Poulose
2017-11-02 14:40       ` Mathieu Poirier
2017-11-02 14:40         ` Mathieu Poirier
2017-11-02 15:13         ` Russell King - ARM Linux
2017-11-02 15:13           ` Russell King - ARM Linux
2017-11-06 19:07   ` Mathieu Poirier
2017-11-06 19:07     ` Mathieu Poirier
2017-11-07 10:36     ` Suzuki K Poulose
2017-11-07 10:36       ` Suzuki K Poulose
2017-11-09 16:19       ` Mathieu Poirier
2017-11-09 16:19         ` Mathieu Poirier
2017-10-19 17:15 ` [PATCH 07/17] coresight: tmc etr: Add transparent buffer management Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-11-02 17:48   ` Mathieu Poirier
2017-11-02 17:48     ` Mathieu Poirier
2017-11-03 10:02     ` Suzuki K Poulose
2017-11-03 10:02       ` Suzuki K Poulose
2017-11-03 20:13       ` Mathieu Poirier
2017-11-03 20:13         ` Mathieu Poirier
2017-10-19 17:15 ` [PATCH 08/17] coresight: tmc: Add configuration support for trace buffer size Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-11-02 19:26   ` Mathieu Poirier
2017-11-02 19:26     ` Mathieu Poirier
2017-10-19 17:15 ` [PATCH 09/17] coresight: Convert driver messages to dev_dbg Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 10/17] coresight: etr: Track if the device is coherent Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-11-02 19:40   ` Mathieu Poirier
2017-11-02 19:40     ` Mathieu Poirier
2017-11-03 10:03     ` Suzuki K Poulose
2017-11-03 10:03       ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 11/17] coresight etr: Handle driver mode specific ETR buffers Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-11-02 20:26   ` Mathieu Poirier
2017-11-02 20:26     ` Mathieu Poirier
2017-11-03 10:08     ` Suzuki K Poulose
2017-11-03 10:08       ` Suzuki K Poulose
2017-11-03 20:30       ` Mathieu Poirier
2017-11-03 20:30         ` Mathieu Poirier
2017-10-19 17:15 ` [PATCH 12/17] coresight etr: Relax collection of trace from sysfs mode Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 13/17] coresight etr: Do not clean ETR trace buffer Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-11-02 20:36   ` Mathieu Poirier [this message]
2017-11-02 20:36     ` Mathieu Poirier
2017-11-03 10:10     ` Suzuki K Poulose
2017-11-03 10:10       ` Suzuki K Poulose
2017-11-03 20:17       ` Mathieu Poirier
2017-11-03 20:17         ` Mathieu Poirier
2017-11-07 10:37         ` Suzuki K Poulose
2017-11-07 10:37           ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 14/17] coresight: etr: Add support for save restore buffers Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-11-03 22:22   ` Mathieu Poirier
2017-11-03 22:22     ` Mathieu Poirier
2017-10-19 17:15 ` [PATCH 15/17] coresight: etr_buf: Add helper for padding an area of trace data Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-10-19 17:15 ` [PATCH 16/17] coresight: perf: Remove reset_buffer call back for sinks Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-11-06 21:10   ` Mathieu Poirier
2017-11-06 21:10     ` Mathieu Poirier
2017-10-19 17:15 ` [PATCH 17/17] coresight perf: Add ETR backend support for etm-perf Suzuki K Poulose
2017-10-19 17:15   ` Suzuki K Poulose
2017-11-07  0:24   ` Mathieu Poirier
2017-11-07  0:24     ` Mathieu Poirier
2017-11-07 10:52     ` Suzuki K Poulose
2017-11-07 10:52       ` Suzuki K Poulose
2017-11-07 15:17       ` Mike Leach
2017-11-07 15:17         ` Mike Leach
2017-11-07 15:46         ` Mathieu Poirier
2017-11-07 15:46           ` Mathieu Poirier
2017-10-20 11:00 ` [PATCH 00/17] coresight: perf: TMC ETR backend support Suzuki K Poulose
2017-10-20 11:00   ` Suzuki K Poulose

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