* [U-Boot] [PATCH 01/11] ARM: DTS: stm32: add pwrcfg node for stm32f746
2017-11-15 12:14 [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver patrice.chotard at st.com
@ 2017-11-15 12:14 ` patrice.chotard at st.com
2017-11-30 15:33 ` [U-Boot] [U-Boot, " Tom Rini
2017-11-15 12:14 ` [U-Boot] [PATCH 02/11] clk: stm32f7: retrieve PWR base address from DT patrice.chotard at st.com
` (10 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: patrice.chotard at st.com @ 2017-11-15 12:14 UTC (permalink / raw)
To: u-boot
From: Patrice Chotard <patrice.chotard@st.com>
This node is needed to enable performance mode
when system frequency is set up to 200Mhz.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
---
arch/arm/dts/stm32f7-u-boot.dtsi | 4 ++++
arch/arm/dts/stm32f746.dtsi | 7 +++++++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi
index 5f77f57..a56ae93 100644
--- a/arch/arm/dts/stm32f7-u-boot.dtsi
+++ b/arch/arm/dts/stm32f7-u-boot.dtsi
@@ -22,3 +22,7 @@
u-boot,dm-pre-reloc;
};
};
+
+&pwrcfg {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 783d4e7..b95cca2 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -99,12 +99,19 @@
status = "disabled";
u-boot,dm-pre-reloc;
};
+
+ pwrcfg: power-config at 58024800 {
+ compatible = "syscon";
+ reg = <0x40007000 0x400>;
+ };
+
rcc: rcc at 40023810 {
#reset-cells = <1>;
#clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
clocks = <&clk_hse>;
+ st,syscfg = <&pwrcfg>;
u-boot,dm-pre-reloc;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH 02/11] clk: stm32f7: retrieve PWR base address from DT
2017-11-15 12:14 [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver patrice.chotard at st.com
2017-11-15 12:14 ` [U-Boot] [PATCH 01/11] ARM: DTS: stm32: add pwrcfg node for stm32f746 patrice.chotard at st.com
@ 2017-11-15 12:14 ` patrice.chotard at st.com
2017-11-30 15:33 ` [U-Boot] [U-Boot, " Tom Rini
2017-11-15 12:14 ` [U-Boot] [PATCH 03/11] clk: stm32f7: add dedicated STM32F7 compatible string patrice.chotard at st.com
` (9 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: patrice.chotard at st.com @ 2017-11-15 12:14 UTC (permalink / raw)
To: u-boot
From: Patrice Chotard <patrice.chotard@st.com>
PWR IP is used to enable over-drive feature in
order to reach a higher frequency.
Get its base address from DT instead of hard-coded value
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
---
arch/arm/include/asm/arch-stm32f4/stm32_pwr.h | 23 +++++++++++++++++++
arch/arm/include/asm/arch-stm32f7/stm32.h | 7 ------
arch/arm/include/asm/arch-stm32f7/stm32_pwr.h | 25 +++++++++++++++++++++
drivers/clk/clk_stm32f7.c | 32 ++++++++++++++++++---------
4 files changed, 69 insertions(+), 18 deletions(-)
create mode 100644 arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
create mode 100644 arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
new file mode 100644
index 0000000..bfe5469
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __STM32_PWR_H_
+
+/*
+ * Offsets of some PWR registers
+ */
+#define PWR_CR1_ODEN BIT(16)
+#define PWR_CR1_ODSWEN BIT(17)
+#define PWR_CSR1_ODRDY BIT(16)
+#define PWR_CSR1_ODSWRDY BIT(17)
+
+struct stm32_pwr_regs {
+ u32 cr1; /* power control register 1 */
+ u32 csr1; /* power control/status register 2 */
+};
+
+#endif /* __STM32_PWR_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index d6412a0..0117039 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -95,13 +95,6 @@ struct stm32_rcc_regs {
};
#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
-struct stm32_pwr_regs {
- u32 cr1; /* power control register 1 */
- u32 csr1; /* power control/status register 2 */
- u32 cr2; /* power control register 2 */
- u32 csr2; /* power control/status register 2 */
-};
-#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE)
void stm32_flash_latency_cfg(int latency);
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
new file mode 100644
index 0000000..917dd46
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __STM32_PWR_H_
+
+/*
+ * Offsets of some PWR registers
+ */
+#define PWR_CR1_ODEN BIT(16)
+#define PWR_CR1_ODSWEN BIT(17)
+#define PWR_CSR1_ODRDY BIT(16)
+#define PWR_CSR1_ODSWRDY BIT(17)
+
+struct stm32_pwr_regs {
+ u32 cr1; /* power control register 1 */
+ u32 csr1; /* power control/status register 2 */
+ u32 cr2; /* power control register 2 */
+ u32 csr2; /* power control/status register 2 */
+};
+
+#endif /* __STM32_PWR_H_ */
diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c
index f1a9e9c..0fa838c 100644
--- a/drivers/clk/clk_stm32f7.c
+++ b/drivers/clk/clk_stm32f7.c
@@ -8,10 +8,12 @@
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
+
#include <asm/io.h>
#include <asm/arch/rcc.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>
+#include <asm/arch/stm32_pwr.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
@@ -52,13 +54,6 @@
#define RCC_CFGR_PPRE1_SHIFT 10
#define RCC_CFGR_PPRE2_SHIFT 13
-/*
- * Offsets of some PWR registers
- */
-#define PWR_CR1_ODEN BIT(16)
-#define PWR_CR1_ODSWEN BIT(17)
-#define PWR_CSR1_ODRDY BIT(16)
-#define PWR_CSR1_ODSWRDY BIT(17)
struct pll_psc {
u8 pll_m;
@@ -88,6 +83,7 @@ struct pll_psc {
struct stm32_clk {
struct stm32_rcc_regs *base;
+ struct stm32_pwr_regs *pwr_regs;
};
#if !defined(CONFIG_STM32_HSE_HZ)
@@ -115,6 +111,7 @@ static int configure_clocks(struct udevice *dev)
{
struct stm32_clk *priv = dev_get_priv(dev);
struct stm32_rcc_regs *regs = priv->base;
+ struct stm32_pwr_regs *pwr = priv->pwr_regs;
/* Reset RCC configuration */
setbits_le32(®s->cr, RCC_CR_HSION);
@@ -153,14 +150,14 @@ static int configure_clocks(struct udevice *dev)
/* Enable high performance mode, System frequency up to 200 MHz */
setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
- setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
+ setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
/* Infinite wait! */
- while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
+ while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
;
/* Enable the Over-drive switch */
- setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
+ setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
/* Infinite wait! */
- while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
+ while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
;
stm32_flash_latency_cfg(5);
@@ -268,6 +265,9 @@ void clock_setup(int peripheral)
static int stm32_clk_probe(struct udevice *dev)
{
+ struct ofnode_phandle_args args;
+ int err;
+
debug("%s: stm32_clk_probe\n", __func__);
struct stm32_clk *priv = dev_get_priv(dev);
@@ -279,6 +279,16 @@ static int stm32_clk_probe(struct udevice *dev)
priv->base = (struct stm32_rcc_regs *)addr;
+ err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
+ &args);
+ if (err) {
+ debug("%s: can't find syscon device (%d)\n", __func__,
+ err);
+ return err;
+ }
+
+ priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
+
configure_clocks(dev);
return 0;
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH 03/11] clk: stm32f7: add dedicated STM32F7 compatible string
2017-11-15 12:14 [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver patrice.chotard at st.com
2017-11-15 12:14 ` [U-Boot] [PATCH 01/11] ARM: DTS: stm32: add pwrcfg node for stm32f746 patrice.chotard at st.com
2017-11-15 12:14 ` [U-Boot] [PATCH 02/11] clk: stm32f7: retrieve PWR base address from DT patrice.chotard at st.com
@ 2017-11-15 12:14 ` patrice.chotard at st.com
2017-11-30 15:33 ` [U-Boot] [U-Boot, " Tom Rini
2017-11-15 12:14 ` [U-Boot] [PATCH 04/11] ARM: DTS: stm32: update rcc compatible for STM32F746 patrice.chotard at st.com
` (8 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: patrice.chotard at st.com @ 2017-11-15 12:14 UTC (permalink / raw)
To: u-boot
From: Patrice Chotard <patrice.chotard@st.com>
Add a dedicated stm32f7 compatible string to use clk_stm32f7
driver with both STM32F4 and STM32F7 SoCs.
It will be needed to manage differences between these 2 SoCs.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
---
drivers/clk/clk_stm32f7.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c
index 0fa838c..eb8a5bf 100644
--- a/drivers/clk/clk_stm32f7.c
+++ b/drivers/clk/clk_stm32f7.c
@@ -319,6 +319,7 @@ static struct clk_ops stm32_clk_ops = {
static const struct udevice_id stm32_clk_ids[] = {
{ .compatible = "st,stm32f42xx-rcc"},
+ { .compatible = "st,stm32f746-rcc"},
{}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH 04/11] ARM: DTS: stm32: update rcc compatible for STM32F746
2017-11-15 12:14 [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver patrice.chotard at st.com
` (2 preceding siblings ...)
2017-11-15 12:14 ` [U-Boot] [PATCH 03/11] clk: stm32f7: add dedicated STM32F7 compatible string patrice.chotard at st.com
@ 2017-11-15 12:14 ` patrice.chotard at st.com
2017-11-30 15:33 ` [U-Boot] [U-Boot, " Tom Rini
2017-11-15 12:14 ` [U-Boot] [PATCH 05/11] clk: stm32f7: add STM32F4 support patrice.chotard at st.com
` (7 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: patrice.chotard at st.com @ 2017-11-15 12:14 UTC (permalink / raw)
To: u-boot
From: Patrice Chotard <patrice.chotard@st.com>
Align the RCC compatible string with the one used by kernel.
It will allow to use the same clock driver for STM32F4
and STM32F7 and to manage the differences between the 2 SoCs
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
---
arch/arm/dts/stm32f746.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index b95cca2..f62360f 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -108,7 +108,7 @@
rcc: rcc at 40023810 {
#reset-cells = <1>;
#clock-cells = <2>;
- compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+ compatible = "st,stm32f746-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
clocks = <&clk_hse>;
st,syscfg = <&pwrcfg>;
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH 05/11] clk: stm32f7: add STM32F4 support
2017-11-15 12:14 [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver patrice.chotard at st.com
` (3 preceding siblings ...)
2017-11-15 12:14 ` [U-Boot] [PATCH 04/11] ARM: DTS: stm32: update rcc compatible for STM32F746 patrice.chotard at st.com
@ 2017-11-15 12:14 ` patrice.chotard at st.com
2017-11-30 15:33 ` [U-Boot] [U-Boot,05/11] " Tom Rini
2017-11-15 12:14 ` [U-Boot] [PATCH 06/11] clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c patrice.chotard at st.com
` (6 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: patrice.chotard at st.com @ 2017-11-15 12:14 UTC (permalink / raw)
To: u-boot
From: Patrice Chotard <patrice.chotard@st.com>
STM32F4 and STM32F7 RCC clock IP are very similar.
Same driver can be used to managed RCC clock for
these 2 SoCs.
Differences between STM32F4 and F7 will be managed using
different compatible string :
_ overdrive clock is only supported by STM32F7
_ different sys_pll_psc parameters can be used between STM32F4
and STM32F7.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
---
drivers/clk/clk_stm32f7.c | 109 ++++++++++++++++++++++++++++------------------
1 file changed, 66 insertions(+), 43 deletions(-)
diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c
index eb8a5bf..4c69740 100644
--- a/drivers/clk/clk_stm32f7.c
+++ b/drivers/clk/clk_stm32f7.c
@@ -81,37 +81,51 @@ struct pll_psc {
#define APB_PSC_8 0x6
#define APB_PSC_16 0x7
+struct stm32_clk_info {
+ struct pll_psc sys_pll_psc;
+ bool has_overdrive;
+};
+
+struct stm32_clk_info stm32f4_clk_info = {
+ /* 180 MHz */
+ .sys_pll_psc = {
+ .pll_m = 8,
+ .pll_n = 360,
+ .pll_p = 2,
+ .pll_q = 8,
+ .ahb_psc = AHB_PSC_1,
+ .apb1_psc = APB_PSC_4,
+ .apb2_psc = APB_PSC_2,
+ },
+ .has_overdrive = false,
+};
+
+struct stm32_clk_info stm32f7_clk_info = {
+ /* 200 MHz */
+ .sys_pll_psc = {
+ .pll_m = 25,
+ .pll_n = 400,
+ .pll_p = 2,
+ .pll_q = 8,
+ .ahb_psc = AHB_PSC_1,
+ .apb1_psc = APB_PSC_4,
+ .apb2_psc = APB_PSC_2,
+ },
+ .has_overdrive = true,
+};
+
struct stm32_clk {
struct stm32_rcc_regs *base;
struct stm32_pwr_regs *pwr_regs;
+ struct stm32_clk_info *info;
};
-#if !defined(CONFIG_STM32_HSE_HZ)
-#error "CONFIG_STM32_HSE_HZ not defined!"
-#else
-#if (CONFIG_STM32_HSE_HZ == 25000000)
-#if (CONFIG_SYS_CLK_FREQ == 200000000)
-/* 200 MHz */
-struct pll_psc sys_pll_psc = {
- .pll_m = 25,
- .pll_n = 400,
- .pll_p = 2,
- .pll_q = 8,
- .ahb_psc = AHB_PSC_1,
- .apb1_psc = APB_PSC_4,
- .apb2_psc = APB_PSC_2
-};
-#endif
-#else
-#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
-#endif
-#endif
-
static int configure_clocks(struct udevice *dev)
{
struct stm32_clk *priv = dev_get_priv(dev);
struct stm32_rcc_regs *regs = priv->base;
struct stm32_pwr_regs *pwr = priv->pwr_regs;
+ struct pll_psc sys_pll_psc = priv->info->sys_pll_psc;
/* Reset RCC configuration */
setbits_le32(®s->cr, RCC_CR_HSION);
@@ -148,17 +162,23 @@ static int configure_clocks(struct udevice *dev)
while (!(readl(®s->cr) & RCC_CR_PLLRDY))
;
- /* Enable high performance mode, System frequency up to 200 MHz */
setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
- setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
- /* Infinite wait! */
- while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
- ;
- /* Enable the Over-drive switch */
- setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
- /* Infinite wait! */
- while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
- ;
+
+ if (priv->info->has_overdrive) {
+ /*
+ * Enable high performance mode
+ * System frequency up to 200 MHz
+ */
+ setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
+ /* Infinite wait! */
+ while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
+ ;
+ /* Enable the Over-drive switch */
+ setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
+ /* Infinite wait! */
+ while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
+ ;
+ }
stm32_flash_latency_cfg(5);
clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
@@ -273,22 +293,25 @@ static int stm32_clk_probe(struct udevice *dev)
struct stm32_clk *priv = dev_get_priv(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = (struct stm32_rcc_regs *)addr;
-
- err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
- &args);
- if (err) {
- debug("%s: can't find syscon device (%d)\n", __func__,
- err);
- return err;
+ priv->info = (struct stm32_clk_info *)dev_get_driver_data(dev);
+
+ if (priv->info->has_overdrive) {
+ err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
+ &args);
+ if (err) {
+ debug("%s: can't find syscon device (%d)\n", __func__,
+ err);
+ return err;
+ }
+
+ priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
}
- priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
-
configure_clocks(dev);
return 0;
@@ -318,8 +341,8 @@ static struct clk_ops stm32_clk_ops = {
};
static const struct udevice_id stm32_clk_ids[] = {
- { .compatible = "st,stm32f42xx-rcc"},
- { .compatible = "st,stm32f746-rcc"},
+ { .compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32f4_clk_info},
+ { .compatible = "st,stm32f746-rcc", .data = (ulong)&stm32f7_clk_info},
{}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH 06/11] clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c
2017-11-15 12:14 [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver patrice.chotard at st.com
` (4 preceding siblings ...)
2017-11-15 12:14 ` [U-Boot] [PATCH 05/11] clk: stm32f7: add STM32F4 support patrice.chotard at st.com
@ 2017-11-15 12:14 ` patrice.chotard at st.com
2017-11-30 15:33 ` [U-Boot] [U-Boot, " Tom Rini
2017-11-15 12:14 ` [U-Boot] [PATCH 07/11] clk: stm32fx: migrate define from rcc.h to driver patrice.chotard at st.com
` (5 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: patrice.chotard at st.com @ 2017-11-15 12:14 UTC (permalink / raw)
To: u-boot
From: Patrice Chotard <patrice.chotard@st.com>
Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs
rename it to a more generic clk_stm32f.c
Fix also some checkpatch errors/warnings.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
---
drivers/clk/Kconfig | 8 ++++++++
drivers/clk/Makefile | 2 +-
drivers/clk/{clk_stm32f7.c => clk_stm32f.c} | 12 ++++--------
3 files changed, 13 insertions(+), 9 deletions(-)
rename drivers/clk/{clk_stm32f7.c => clk_stm32f.c} (98%)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index baa60a5..f6644ee 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -46,6 +46,14 @@ config CLK_BOSTON
help
Enable this to support the clocks
+config CLK_STM32F
+ bool "Enable clock driver support for STM32F family"
+ depends on CLK && (STM32F7 || STM32F4)
+ default y
+ help
+ This clock driver adds support for RCC clock management
+ for STM32F4 and STM32F7 SoCs.
+
config CLK_ZYNQ
bool "Enable clock driver support for Zynq"
depends on CLK && ARCH_ZYNQ
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 83fe88c..bcc8f82 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -21,5 +21,5 @@ obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
-obj-$(CONFIG_STM32F7) += clk_stm32f7.o
+obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f.c
similarity index 98%
rename from drivers/clk/clk_stm32f7.c
rename to drivers/clk/clk_stm32f.c
index 4c69740..10f4485 100644
--- a/drivers/clk/clk_stm32f7.c
+++ b/drivers/clk/clk_stm32f.c
@@ -197,6 +197,7 @@ static unsigned long stm32_clk_get_rate(struct clk *clk)
struct stm32_rcc_regs *regs = priv->base;
u32 sysclk = 0;
u32 shift = 0;
+ u16 pllm, plln, pllp;
/* Prescaler table lookups for clock computation */
u8 ahb_psc_table[16] = {
0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
@@ -207,7 +208,6 @@ static unsigned long stm32_clk_get_rate(struct clk *clk)
if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
RCC_CFGR_SWS_PLL) {
- u16 pllm, plln, pllp;
pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
>> RCC_PLLCFGR_PLLN_SHIFT);
@@ -228,25 +228,21 @@ static unsigned long stm32_clk_get_rate(struct clk *clk)
(readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
>> RCC_CFGR_HPRE_SHIFT)];
return sysclk >>= shift;
- break;
/* APB1 CLOCK */
case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
shift = apb_psc_table[(
(readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
>> RCC_CFGR_PPRE1_SHIFT)];
return sysclk >>= shift;
- break;
/* APB2 CLOCK */
case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
shift = apb_psc_table[(
(readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
>> RCC_CFGR_PPRE2_SHIFT)];
return sysclk >>= shift;
- break;
default:
pr_err("clock index %ld out of range\n", clk->id);
return -EINVAL;
- break;
}
}
@@ -288,7 +284,7 @@ static int stm32_clk_probe(struct udevice *dev)
struct ofnode_phandle_args args;
int err;
- debug("%s: stm32_clk_probe\n", __func__);
+ debug("%s\n", __func__);
struct stm32_clk *priv = dev_get_priv(dev);
fdt_addr_t addr;
@@ -346,8 +342,8 @@ static const struct udevice_id stm32_clk_ids[] = {
{}
};
-U_BOOT_DRIVER(stm32f7_clk) = {
- .name = "stm32f7_clk",
+U_BOOT_DRIVER(stm32fx_clk) = {
+ .name = "stm32fx_clk",
.id = UCLASS_CLK,
.of_match = stm32_clk_ids,
.ops = &stm32_clk_ops,
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH 07/11] clk: stm32fx: migrate define from rcc.h to driver
2017-11-15 12:14 [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver patrice.chotard at st.com
` (5 preceding siblings ...)
2017-11-15 12:14 ` [U-Boot] [PATCH 06/11] clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c patrice.chotard at st.com
@ 2017-11-15 12:14 ` patrice.chotard at st.com
2017-11-30 15:34 ` [U-Boot] [U-Boot, " Tom Rini
2017-11-15 12:14 ` [U-Boot] [PATCH 08/11] configs: stm32f746-disco: enable MISC/DM_RESET/STM32_RESET and STM32_RCC patrice.chotard at st.com
` (4 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: patrice.chotard at st.com @ 2017-11-15 12:14 UTC (permalink / raw)
To: u-boot
From: Patrice Chotard <patrice.chotard@st.com>
STM32F4 doesn't get rcc.h file, to avoid compilation
issue, migrate RCC related defines from rcc.h to driver
file and remove rcc.h file.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
---
arch/arm/include/asm/arch-stm32f7/rcc.h | 31 -------------------------------
drivers/clk/clk_stm32f.c | 19 ++++++++++++++++++-
2 files changed, 18 insertions(+), 32 deletions(-)
delete mode 100644 arch/arm/include/asm/arch-stm32f7/rcc.h
diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h
deleted file mode 100644
index 6475f9d..0000000
--- a/arch/arm/include/asm/arch-stm32f7/rcc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _STM32_RCC_H
-#define _STM32_RCC_H
-
-#include <dt-bindings/mfd/stm32f7-rcc.h>
-
-/*
- * RCC AHB1ENR specific definitions
- */
-#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
-#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
-#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
-
-/*
- * RCC APB1ENR specific definitions
- */
-#define RCC_APB1ENR_TIM2EN BIT(0)
-#define RCC_APB1ENR_PWREN BIT(28)
-
-/*
- * RCC APB2ENR specific definitions
- */
-#define RCC_APB2ENR_SYSCFGEN BIT(14)
-
-#endif
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index 10f4485..c7af7a1 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -10,7 +10,6 @@
#include <dm.h>
#include <asm/io.h>
-#include <asm/arch/rcc.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>
#include <asm/arch/stm32_pwr.h>
@@ -54,6 +53,24 @@
#define RCC_CFGR_PPRE1_SHIFT 10
#define RCC_CFGR_PPRE2_SHIFT 13
+/*
+ * RCC AHB1ENR specific definitions
+ */
+#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
+#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
+#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
+
+/*
+ * RCC APB1ENR specific definitions
+ */
+#define RCC_APB1ENR_TIM2EN BIT(0)
+#define RCC_APB1ENR_PWREN BIT(28)
+
+/*
+ * RCC APB2ENR specific definitions
+ */
+#define RCC_APB2ENR_SYSCFGEN BIT(14)
+
struct pll_psc {
u8 pll_m;
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH 08/11] configs: stm32f746-disco: enable MISC/DM_RESET/STM32_RESET and STM32_RCC
2017-11-15 12:14 [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver patrice.chotard at st.com
` (6 preceding siblings ...)
2017-11-15 12:14 ` [U-Boot] [PATCH 07/11] clk: stm32fx: migrate define from rcc.h to driver patrice.chotard at st.com
@ 2017-11-15 12:14 ` patrice.chotard at st.com
2017-11-30 15:34 ` [U-Boot] [U-Boot, " Tom Rini
2017-11-15 12:14 ` [U-Boot] [PATCH 09/11] dm: misc: bind STM32F4/F7 clock from rcc MFD driver patrice.chotard at st.com
` (3 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: patrice.chotard at st.com @ 2017-11-15 12:14 UTC (permalink / raw)
To: u-boot
From: Patrice Chotard <patrice.chotard@st.com>
This allows to add rcc MFD support to stm32f746-disco board
This rcc MFD driver manages clock and reset for STM32 SoCs family
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
---
configs/stm32f746-disco_defconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index e78a43d..53bfd9d 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -31,6 +31,8 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_CLK=y
CONFIG_DM_GPIO=y
+CONFIG_MISC=y
+CONFIG_STM32_RCC=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
@@ -44,6 +46,8 @@ CONFIG_PINCTRL=y
CONFIG_PINCTRL_STM32=y
CONFIG_RAM=y
CONFIG_STM32_SDRAM=y
+CONFIG_DM_RESET=y
+CONFIG_STM32_RESET=y
CONFIG_STM32X7_SERIAL=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH 09/11] dm: misc: bind STM32F4/F7 clock from rcc MFD driver
2017-11-15 12:14 [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver patrice.chotard at st.com
` (7 preceding siblings ...)
2017-11-15 12:14 ` [U-Boot] [PATCH 08/11] configs: stm32f746-disco: enable MISC/DM_RESET/STM32_RESET and STM32_RCC patrice.chotard at st.com
@ 2017-11-15 12:14 ` patrice.chotard at st.com
2017-11-30 15:34 ` [U-Boot] [U-Boot, " Tom Rini
2017-11-15 12:14 ` [U-Boot] [PATCH 10/11] clk: clk_stm32fx: add clock configuration for mmc usage patrice.chotard at st.com
` (2 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: patrice.chotard at st.com @ 2017-11-15 12:14 UTC (permalink / raw)
To: u-boot
From: Patrice Chotard <patrice.chotard@st.com>
Like STM32H7, now STM32F4/F7 clock drivers are binded by
MFD stm32_rcc driver.
This also allows to add reset support to STM32F4/F7 SoCs family.
As Reset driver is not part of SPL supported drivers, don't bind it
in case of SPL to avoid that stm32_rcc_bind() returns an error.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
---
drivers/clk/clk_stm32f.c | 54 ++++++++++++------------------------------------
drivers/misc/stm32_rcc.c | 42 ++++++++++++++++++++++++++++++++-----
include/stm32_rcc.h | 52 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 102 insertions(+), 46 deletions(-)
create mode 100644 include/stm32_rcc.h
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index c7af7a1..6e29c55 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
+#include <stm32_rcc.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
@@ -71,38 +72,6 @@
*/
#define RCC_APB2ENR_SYSCFGEN BIT(14)
-
-struct pll_psc {
- u8 pll_m;
- u16 pll_n;
- u8 pll_p;
- u8 pll_q;
- u8 ahb_psc;
- u8 apb1_psc;
- u8 apb2_psc;
-};
-
-#define AHB_PSC_1 0
-#define AHB_PSC_2 0x8
-#define AHB_PSC_4 0x9
-#define AHB_PSC_8 0xA
-#define AHB_PSC_16 0xB
-#define AHB_PSC_64 0xC
-#define AHB_PSC_128 0xD
-#define AHB_PSC_256 0xE
-#define AHB_PSC_512 0xF
-
-#define APB_PSC_1 0
-#define APB_PSC_2 0x4
-#define APB_PSC_4 0x5
-#define APB_PSC_8 0x6
-#define APB_PSC_16 0x7
-
-struct stm32_clk_info {
- struct pll_psc sys_pll_psc;
- bool has_overdrive;
-};
-
struct stm32_clk_info stm32f4_clk_info = {
/* 180 MHz */
.sys_pll_psc = {
@@ -311,7 +280,17 @@ static int stm32_clk_probe(struct udevice *dev)
return -EINVAL;
priv->base = (struct stm32_rcc_regs *)addr;
- priv->info = (struct stm32_clk_info *)dev_get_driver_data(dev);
+
+ switch (dev_get_driver_data(dev)) {
+ case STM32F4:
+ priv->info = &stm32f4_clk_info;
+ break;
+ case STM32F7:
+ priv->info = &stm32f7_clk_info;
+ break;
+ default:
+ return -EINVAL;
+ }
if (priv->info->has_overdrive) {
err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
@@ -353,16 +332,9 @@ static struct clk_ops stm32_clk_ops = {
.get_rate = stm32_clk_get_rate,
};
-static const struct udevice_id stm32_clk_ids[] = {
- { .compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32f4_clk_info},
- { .compatible = "st,stm32f746-rcc", .data = (ulong)&stm32f7_clk_info},
- {}
-};
-
U_BOOT_DRIVER(stm32fx_clk) = {
- .name = "stm32fx_clk",
+ .name = "stm32fx_rcc_clock",
.id = UCLASS_CLK,
- .of_match = stm32_clk_ids,
.ops = &stm32_clk_ops,
.probe = stm32_clk_probe,
.priv_auto_alloc_size = sizeof(struct stm32_clk),
diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c
index 32d3971..87d9928 100644
--- a/drivers/misc/stm32_rcc.c
+++ b/drivers/misc/stm32_rcc.c
@@ -8,31 +8,63 @@
#include <common.h>
#include <dm.h>
#include <misc.h>
+#include <stm32_rcc.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
+struct stm32_rcc_clk stm32_rcc_clk_f4 = {
+ .drv_name = "stm32fx_rcc_clock",
+ .soc = STM32F4,
+};
+
+struct stm32_rcc_clk stm32_rcc_clk_f7 = {
+ .drv_name = "stm32fx_rcc_clock",
+ .soc = STM32F7,
+};
+
+struct stm32_rcc_clk stm32_rcc_clk_h7 = {
+ .drv_name = "stm32h7_rcc_clock",
+};
+
static int stm32_rcc_bind(struct udevice *dev)
{
- int ret;
struct udevice *child;
+ struct driver *drv;
+ struct stm32_rcc_clk *rcc_clk =
+ (struct stm32_rcc_clk *)dev_get_driver_data(dev);
+ int ret;
debug("%s(dev=%p)\n", __func__, dev);
- ret = device_bind_driver_to_node(dev, "stm32h7_rcc_clock",
- "stm32h7_rcc_clock",
- dev_ofnode(dev), &child);
+ drv = lists_driver_lookup_name(rcc_clk->drv_name);
+ if (!drv) {
+ debug("Cannot find driver '%s'\n", rcc_clk->drv_name);
+ return -ENOENT;
+ }
+
+ ret = device_bind_with_driver_data(dev, drv, rcc_clk->drv_name,
+ rcc_clk->soc,
+ dev_ofnode(dev), &child);
+
if (ret)
return ret;
+#ifdef CONFIG_SPL_BUILD
+ return 0;
+#else
return device_bind_driver_to_node(dev, "stm32_rcc_reset",
"stm32_rcc_reset",
dev_ofnode(dev), &child);
+#endif
}
static const struct misc_ops stm32_rcc_ops = {
};
static const struct udevice_id stm32_rcc_ids[] = {
- {.compatible = "st,stm32h743-rcc"},
+ {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f4 },
+ {.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 },
+ {.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 },
{ }
};
diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h
new file mode 100644
index 0000000..6dfb9cc
--- /dev/null
+++ b/include/stm32_rcc.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __STM32_RCC_H_
+#define __STM32_RCC_H_
+
+#define AHB_PSC_1 0
+#define AHB_PSC_2 0x8
+#define AHB_PSC_4 0x9
+#define AHB_PSC_8 0xA
+#define AHB_PSC_16 0xB
+#define AHB_PSC_64 0xC
+#define AHB_PSC_128 0xD
+#define AHB_PSC_256 0xE
+#define AHB_PSC_512 0xF
+
+#define APB_PSC_1 0
+#define APB_PSC_2 0x4
+#define APB_PSC_4 0x5
+#define APB_PSC_8 0x6
+#define APB_PSC_16 0x7
+
+struct pll_psc {
+ u8 pll_m;
+ u16 pll_n;
+ u8 pll_p;
+ u8 pll_q;
+ u8 ahb_psc;
+ u8 apb1_psc;
+ u8 apb2_psc;
+};
+
+struct stm32_clk_info {
+ struct pll_psc sys_pll_psc;
+ bool has_overdrive;
+};
+
+enum soc_family {
+ STM32F4,
+ STM32F7,
+};
+
+struct stm32_rcc_clk {
+ char *drv_name;
+ enum soc_family soc;
+};
+
+#endif /* __STM32_RCC_H_ */
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH 10/11] clk: clk_stm32fx: add clock configuration for mmc usage
2017-11-15 12:14 [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver patrice.chotard at st.com
` (8 preceding siblings ...)
2017-11-15 12:14 ` [U-Boot] [PATCH 09/11] dm: misc: bind STM32F4/F7 clock from rcc MFD driver patrice.chotard at st.com
@ 2017-11-15 12:14 ` patrice.chotard at st.com
2017-11-30 15:34 ` [U-Boot] [U-Boot, " Tom Rini
2017-11-15 12:14 ` [U-Boot] [PATCH 11/11] stm32: migrate clock structs in include/stm32_rcc.h patrice.chotard at st.com
2017-11-15 17:35 ` [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver Vikas Manocha
11 siblings, 1 reply; 24+ messages in thread
From: patrice.chotard at st.com @ 2017-11-15 12:14 UTC (permalink / raw)
To: u-boot
From: Patrice Chotard <patrice.chotard@st.com>
MMC block needs 48Mhz source clock, for that we choose
to select the SAI PLL.
Update also stm32_clock_get_rate() to retrieve the MMC
clock source needed in MMC driver.
STM32F4 uses a different RCC variant than STM32F7. For STM32F4
sdmmc clocks bit are located into dckcfgr register whereas there
are located into dckcfgr2 registers on STM32F7.
In both registers, bits CK48MSEL and SDMMC1SEL are located at
the same position.
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
---
arch/arm/include/asm/arch-stm32f7/stm32.h | 1 +
drivers/clk/clk_stm32f.c | 101 +++++++++++++++++++++++++++++-
include/dt-bindings/mfd/stm32f7-rcc.h | 1 +
include/stm32_rcc.h | 1 +
4 files changed, 103 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index 0117039..f5e08ef 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -92,6 +92,7 @@ struct stm32_rcc_regs {
u32 plli2scfgr; /* RCC PLLI2S configuration */
u32 pllsaicfgr; /* PLLSAI configuration */
u32 dckcfgr; /* dedicated clocks configuration register */
+ u32 dckcfgr2; /* dedicated clocks configuration register */
};
#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index 6e29c55..634f071 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -24,6 +24,8 @@
#define RCC_CR_CSSON BIT(19)
#define RCC_CR_PLLON BIT(24)
#define RCC_CR_PLLRDY BIT(25)
+#define RCC_CR_PLLSAION BIT(28)
+#define RCC_CR_PLLSAIRDY BIT(29)
#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
@@ -54,6 +56,20 @@
#define RCC_CFGR_PPRE1_SHIFT 10
#define RCC_CFGR_PPRE2_SHIFT 13
+#define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6)
+#define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16)
+#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
+#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
+#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(17)
+#define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
+#define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29)
+
+#define RCC_DCKCFGRX_CK48MSEL BIT(27)
+#define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
+#define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
+
+#define RCC_APB2ENR_SAI1EN BIT(22)
+
/*
* RCC AHB1ENR specific definitions
*/
@@ -84,6 +100,7 @@ struct stm32_clk_info stm32f4_clk_info = {
.apb2_psc = APB_PSC_2,
},
.has_overdrive = false,
+ .v2 = false,
};
struct stm32_clk_info stm32f7_clk_info = {
@@ -98,6 +115,7 @@ struct stm32_clk_info stm32f7_clk_info = {
.apb2_psc = APB_PSC_2,
},
.has_overdrive = true,
+ .v2 = true,
};
struct stm32_clk {
@@ -112,12 +130,13 @@ static int configure_clocks(struct udevice *dev)
struct stm32_rcc_regs *regs = priv->base;
struct stm32_pwr_regs *pwr = priv->pwr_regs;
struct pll_psc sys_pll_psc = priv->info->sys_pll_psc;
+ u32 pllsaicfgr = 0;
/* Reset RCC configuration */
setbits_le32(®s->cr, RCC_CR_HSION);
writel(0, ®s->cfgr); /* Reset CFGR */
clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON
- | RCC_CR_PLLON));
+ | RCC_CR_PLLON | RCC_CR_PLLSAION));
writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */
clrbits_le32(®s->cr, RCC_CR_HSEBYP);
writel(0, ®s->cir); /* Disable all interrupts */
@@ -143,11 +162,39 @@ static int configure_clocks(struct udevice *dev)
clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
+ /* Configure the SAI PLL to get a 48 MHz source */
+ pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 |
+ RCC_PLLSAICFGR_PLLSAIP_4;
+ pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT;
+ writel(pllsaicfgr, ®s->pllsaicfgr);
+
/* Enable the main PLL */
setbits_le32(®s->cr, RCC_CR_PLLON);
while (!(readl(®s->cr) & RCC_CR_PLLRDY))
;
+ if (priv->info->v2) { /*stm32f7 case */
+ /* select PLLSAI as 48MHz clock source */
+ setbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
+
+ /* select 48MHz as SDMMC1 clock source */
+ clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
+
+ /* select 48MHz as SDMMC2 clock source */
+ clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
+ } else { /* stm32f4 case */
+ /* select PLLSAI as 48MHz clock source */
+ setbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
+
+ /* select 48MHz as SDMMC1 clock source */
+ clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
+ }
+
+ /* Enable the SAI PLL */
+ setbits_le32(®s->cr, RCC_CR_PLLSAION);
+ while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY))
+ ;
+
setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
if (priv->info->has_overdrive) {
@@ -173,10 +220,40 @@ static int configure_clocks(struct udevice *dev)
while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL)
;
+ /* gate the SAI clock, needed for MMC 1&2 clocks */
+ setbits_le32(®s->apb2enr, RCC_APB2ENR_SAI1EN);
return 0;
}
+static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
+ u32 sysclk)
+{
+ struct stm32_rcc_regs *regs = priv->base;
+ u16 pllq, pllm, pllsain, pllsaip;
+ bool pllsai;
+
+ pllq = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
+ >> RCC_PLLCFGR_PLLQ_SHIFT;
+
+ if (priv->info->v2) /*stm32f7 case */
+ pllsai = readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
+ else
+ pllsai = readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
+
+ if (pllsai) {
+ /* PLL48CLK is selected from PLLSAI, get PLLSAI value */
+ pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
+ pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK)
+ >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
+ pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK)
+ >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
+ return ((CONFIG_STM32_HSE_HZ / pllm) * pllsain) / pllsaip;
+ }
+ /* PLL48CLK is selected from PLLQ */
+ return sysclk / pllq;
+}
+
static unsigned long stm32_clk_get_rate(struct clk *clk)
{
struct stm32_clk *priv = dev_get_priv(clk->dev);
@@ -222,6 +299,28 @@ static unsigned long stm32_clk_get_rate(struct clk *clk)
return sysclk >>= shift;
/* APB2 CLOCK */
case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
+ /*
+ * particular case for SDMMC1 and SDMMC2 :
+ * 48Mhz source clock can be from main PLL or from
+ * SAI PLL
+ */
+ switch (clk->id) {
+ case STM32F7_APB2_CLOCK(SDMMC1):
+ if (readl(®s->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL)
+ /* System clock is selected as SDMMC1 clock */
+ return sysclk;
+ else
+ return stm32_clk_pll48clk_rate(priv, sysclk);
+ break;
+ case STM32F7_APB2_CLOCK(SDMMC2):
+ if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL)
+ /* System clock is selected as SDMMC2 clock */
+ return sysclk;
+ else
+ return stm32_clk_pll48clk_rate(priv, sysclk);
+ break;
+ }
+
shift = apb_psc_table[(
(readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
>> RCC_CFGR_PPRE2_SHIFT)];
diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h
index e36cc69..44c0914 100644
--- a/include/dt-bindings/mfd/stm32f7-rcc.h
+++ b/include/dt-bindings/mfd/stm32f7-rcc.h
@@ -90,6 +90,7 @@
#define STM32F7_RCC_APB2_TIM8 1
#define STM32F7_RCC_APB2_USART1 4
#define STM32F7_RCC_APB2_USART6 5
+#define STM32F7_RCC_APB2_SDMMC2 7
#define STM32F7_RCC_APB2_ADC1 8
#define STM32F7_RCC_APB2_ADC2 9
#define STM32F7_RCC_APB2_ADC3 10
diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h
index 6dfb9cc..fb08552 100644
--- a/include/stm32_rcc.h
+++ b/include/stm32_rcc.h
@@ -37,6 +37,7 @@ struct pll_psc {
struct stm32_clk_info {
struct pll_psc sys_pll_psc;
bool has_overdrive;
+ bool v2;
};
enum soc_family {
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [U-Boot, 10/11] clk: clk_stm32fx: add clock configuration for mmc usage
2017-11-15 12:14 ` [U-Boot] [PATCH 10/11] clk: clk_stm32fx: add clock configuration for mmc usage patrice.chotard at st.com
@ 2017-11-30 15:34 ` Tom Rini
0 siblings, 0 replies; 24+ messages in thread
From: Tom Rini @ 2017-11-30 15:34 UTC (permalink / raw)
To: u-boot
On Wed, Nov 15, 2017 at 01:14:52PM +0100, patrice.chotard at st.com wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> MMC block needs 48Mhz source clock, for that we choose
> to select the SAI PLL.
> Update also stm32_clock_get_rate() to retrieve the MMC
> clock source needed in MMC driver.
>
> STM32F4 uses a different RCC variant than STM32F7. For STM32F4
> sdmmc clocks bit are located into dckcfgr register whereas there
> are located into dckcfgr2 registers on STM32F7.
> In both registers, bits CK48MSEL and SDMMC1SEL are located at
> the same position.
>
> Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 11/11] stm32: migrate clock structs in include/stm32_rcc.h
2017-11-15 12:14 [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver patrice.chotard at st.com
` (9 preceding siblings ...)
2017-11-15 12:14 ` [U-Boot] [PATCH 10/11] clk: clk_stm32fx: add clock configuration for mmc usage patrice.chotard at st.com
@ 2017-11-15 12:14 ` patrice.chotard at st.com
2017-11-30 15:34 ` [U-Boot] [U-Boot, " Tom Rini
2017-11-15 17:35 ` [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver Vikas Manocha
11 siblings, 1 reply; 24+ messages in thread
From: patrice.chotard at st.com @ 2017-11-15 12:14 UTC (permalink / raw)
To: u-boot
From: Patrice Chotard <patrice.chotard@st.com>
In order to factorize code between STM32F4 and STM32F7
migrate all structs related to RCC clocks in include/stm32_rcc.h
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
---
arch/arm/include/asm/arch-stm32f4/stm32.h | 35 --------------------
arch/arm/include/asm/arch-stm32f7/stm32.h | 35 --------------------
arch/arm/mach-stm32/stm32f4/clock.c | 27 +--------------
arch/arm/mach-stm32/stm32f4/timer.c | 1 +
arch/arm/mach-stm32/stm32f7/timer.c | 1 +
board/st/stm32f429-discovery/stm32f429-discovery.c | 1 +
include/stm32_rcc.h | 38 ++++++++++++++++++++++
7 files changed, 42 insertions(+), 96 deletions(-)
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
index 6cc1966..e9f3aab 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -42,41 +42,6 @@ struct stm32_u_id_regs {
u32 u_id_high;
};
-struct stm32_rcc_regs {
- u32 cr; /* RCC clock control */
- u32 pllcfgr; /* RCC PLL configuration */
- u32 cfgr; /* RCC clock configuration */
- u32 cir; /* RCC clock interrupt */
- u32 ahb1rstr; /* RCC AHB1 peripheral reset */
- u32 ahb2rstr; /* RCC AHB2 peripheral reset */
- u32 ahb3rstr; /* RCC AHB3 peripheral reset */
- u32 rsv0;
- u32 apb1rstr; /* RCC APB1 peripheral reset */
- u32 apb2rstr; /* RCC APB2 peripheral reset */
- u32 rsv1[2];
- u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
- u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
- u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
- u32 rsv2;
- u32 apb1enr; /* RCC APB1 peripheral clock enable */
- u32 apb2enr; /* RCC APB2 peripheral clock enable */
- u32 rsv3[2];
- u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
- u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
- u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
- u32 rsv4;
- u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
- u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
- u32 rsv5[2];
- u32 bdcr; /* RCC Backup domain control */
- u32 csr; /* RCC clock control & status */
- u32 rsv6[2];
- u32 sscgr; /* RCC spread spectrum clock generation */
- u32 plli2scfgr; /* RCC PLLI2S configuration */
- u32 pllsaicfgr;
- u32 dckcfgr;
-};
-
struct stm32_pwr_regs {
u32 cr;
u32 csr;
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index f5e08ef..f54e6f1 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -59,41 +59,6 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
#define STM32_BUS_MASK GENMASK(31, 16)
-struct stm32_rcc_regs {
- u32 cr; /* RCC clock control */
- u32 pllcfgr; /* RCC PLL configuration */
- u32 cfgr; /* RCC clock configuration */
- u32 cir; /* RCC clock interrupt */
- u32 ahb1rstr; /* RCC AHB1 peripheral reset */
- u32 ahb2rstr; /* RCC AHB2 peripheral reset */
- u32 ahb3rstr; /* RCC AHB3 peripheral reset */
- u32 rsv0;
- u32 apb1rstr; /* RCC APB1 peripheral reset */
- u32 apb2rstr; /* RCC APB2 peripheral reset */
- u32 rsv1[2];
- u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
- u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
- u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
- u32 rsv2;
- u32 apb1enr; /* RCC APB1 peripheral clock enable */
- u32 apb2enr; /* RCC APB2 peripheral clock enable */
- u32 rsv3[2];
- u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
- u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
- u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
- u32 rsv4;
- u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
- u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
- u32 rsv5[2];
- u32 bdcr; /* RCC Backup domain control */
- u32 csr; /* RCC clock control & status */
- u32 rsv6[2];
- u32 sscgr; /* RCC spread spectrum clock generation */
- u32 plli2scfgr; /* RCC PLLI2S configuration */
- u32 pllsaicfgr; /* PLLSAI configuration */
- u32 dckcfgr; /* dedicated clocks configuration register */
- u32 dckcfgr2; /* dedicated clocks configuration register */
-};
#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c
index 15fcadb..774591d 100644
--- a/arch/arm/mach-stm32/stm32f4/clock.c
+++ b/arch/arm/mach-stm32/stm32f4/clock.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <stm32_rcc.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>
@@ -81,32 +82,6 @@
#define RCC_ENR_GPIO_J_EN (1 << 9)
#define RCC_ENR_GPIO_K_EN (1 << 10)
-struct pll_psc {
- u8 pll_m;
- u16 pll_n;
- u8 pll_p;
- u8 pll_q;
- u8 ahb_psc;
- u8 apb1_psc;
- u8 apb2_psc;
-};
-
-#define AHB_PSC_1 0
-#define AHB_PSC_2 0x8
-#define AHB_PSC_4 0x9
-#define AHB_PSC_8 0xA
-#define AHB_PSC_16 0xB
-#define AHB_PSC_64 0xC
-#define AHB_PSC_128 0xD
-#define AHB_PSC_256 0xE
-#define AHB_PSC_512 0xF
-
-#define APB_PSC_1 0
-#define APB_PSC_2 0x4
-#define APB_PSC_4 0x5
-#define APB_PSC_8 0x6
-#define APB_PSC_16 0x7
-
#if !defined(CONFIG_STM32_HSE_HZ)
#error "CONFIG_STM32_HSE_HZ not defined!"
#else
diff --git a/arch/arm/mach-stm32/stm32f4/timer.c b/arch/arm/mach-stm32/stm32f4/timer.c
index 1dee190..163f461 100644
--- a/arch/arm/mach-stm32/stm32f4/timer.c
+++ b/arch/arm/mach-stm32/stm32f4/timer.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <stm32_rcc.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
diff --git a/arch/arm/mach-stm32/stm32f7/timer.c b/arch/arm/mach-stm32/stm32f7/timer.c
index 0521c24..69d37a7 100644
--- a/arch/arm/mach-stm32/stm32f7/timer.c
+++ b/arch/arm/mach-stm32/stm32f7/timer.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <stm32_rcc.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_defs.h>
diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c
index d6763c3..6f19a05 100644
--- a/board/st/stm32f429-discovery/stm32f429-discovery.c
+++ b/board/st/stm32f429-discovery/stm32f429-discovery.c
@@ -13,6 +13,7 @@
#include <common.h>
#include <dm.h>
+#include <stm32_rcc.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h
index fb08552..063177b 100644
--- a/include/stm32_rcc.h
+++ b/include/stm32_rcc.h
@@ -50,4 +50,42 @@ struct stm32_rcc_clk {
enum soc_family soc;
};
+struct stm32_rcc_regs {
+ u32 cr; /* RCC clock control */
+ u32 pllcfgr; /* RCC PLL configuration */
+ u32 cfgr; /* RCC clock configuration */
+ u32 cir; /* RCC clock interrupt */
+ u32 ahb1rstr; /* RCC AHB1 peripheral reset */
+ u32 ahb2rstr; /* RCC AHB2 peripheral reset */
+ u32 ahb3rstr; /* RCC AHB3 peripheral reset */
+ u32 rsv0;
+ u32 apb1rstr; /* RCC APB1 peripheral reset */
+ u32 apb2rstr; /* RCC APB2 peripheral reset */
+ u32 rsv1[2];
+ u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
+ u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
+ u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
+ u32 rsv2;
+ u32 apb1enr; /* RCC APB1 peripheral clock enable */
+ u32 apb2enr; /* RCC APB2 peripheral clock enable */
+ u32 rsv3[2];
+ u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
+ u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
+ u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
+ u32 rsv4;
+ u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
+ u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
+ u32 rsv5[2];
+ u32 bdcr; /* RCC Backup domain control */
+ u32 csr; /* RCC clock control & status */
+ u32 rsv6[2];
+ u32 sscgr; /* RCC spread spectrum clock generation */
+ u32 plli2scfgr; /* RCC PLLI2S configuration */
+ /* below registers are only available on STM32F46x and STM32F7 SoCs*/
+ u32 pllsaicfgr; /* PLLSAI configuration */
+ u32 dckcfgr; /* dedicated clocks configuration register */
+ /* Below registers are only available on STM32F7 SoCs */
+ u32 dckcfgr2; /* dedicated clocks configuration register */
+};
+
#endif /* __STM32_RCC_H_ */
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver
2017-11-15 12:14 [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver patrice.chotard at st.com
` (10 preceding siblings ...)
2017-11-15 12:14 ` [U-Boot] [PATCH 11/11] stm32: migrate clock structs in include/stm32_rcc.h patrice.chotard at st.com
@ 2017-11-15 17:35 ` Vikas Manocha
11 siblings, 0 replies; 24+ messages in thread
From: Vikas Manocha @ 2017-11-15 17:35 UTC (permalink / raw)
To: u-boot
LGTM.
Cheers,
Vikas
On 11/15/2017 04:14 AM, patrice.chotard at st.com wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> It's the second step to prepare STM32F4 conversion to driver model and
> device tree support. STM32F4 and STM32F7 RCC IPs are similar, differences
> between these 2 SoCs can be managed with different compatible string and
> allows to use a common clock driver.
>
> This series update the clk_stm32f7 driver :
> _ retrieve PWR IP base address from DT instead of using hardcoded value.
> _ update compatible string to manage differences between STM32F4 and
> STM32F7
> _ introduce STM32F4 support.
> _ enable RCC MFD support which allows reset support for STM32F7/F4.
> _ add MMC clock configuration for MMC usag for STM32F4/F7.
> _ migrate some defines/struct to common include/stm32_rcc.h to
> factorize code between STM32F4/F7.
>
> Patrice Chotard (11):
> ARM: DTS: stm32: add pwrcfg node for stm32f746
> clk: stm32f7: retrieve PWR base address from DT
> clk: stm32f7: add dedicated STM32F7 compatible string
> ARM: DTS: stm32: update rcc compatible for STM32F746
> clk: stm32f7: add STM32F4 support
> clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c
> clk: stm32fx: migrate define from rcc.h to driver
> configs: stm32f746-disco: enable MISC/DM_RESET/STM32_RESET and
> STM32_RCC
> dm: misc: bind STM32F4/F7 clock from rcc MFD driver
> clk: clk_stm32fx: add clock configuration for mmc usage
> stm32: migrate clock structs in include/stm32_rcc.h
>
> arch/arm/dts/stm32f7-u-boot.dtsi | 4 +
> arch/arm/dts/stm32f746.dtsi | 9 +-
> arch/arm/include/asm/arch-stm32f4/stm32.h | 35 ---
> arch/arm/include/asm/arch-stm32f4/stm32_pwr.h | 23 ++
> arch/arm/include/asm/arch-stm32f7/rcc.h | 31 ---
> arch/arm/include/asm/arch-stm32f7/stm32.h | 41 ----
> arch/arm/include/asm/arch-stm32f7/stm32_pwr.h | 25 ++
> arch/arm/mach-stm32/stm32f4/clock.c | 27 +-
> arch/arm/mach-stm32/stm32f4/timer.c | 1 +
> arch/arm/mach-stm32/stm32f7/timer.c | 1 +
> board/st/stm32f429-discovery/stm32f429-discovery.c | 1 +
> configs/stm32f746-disco_defconfig | 4 +
> drivers/clk/Kconfig | 8 +
> drivers/clk/Makefile | 2 +-
> drivers/clk/{clk_stm32f7.c => clk_stm32f.c} | 272 +++++++++++++++------
> drivers/misc/stm32_rcc.c | 42 +++-
> include/dt-bindings/mfd/stm32f7-rcc.h | 1 +
> include/stm32_rcc.h | 91 +++++++
> 18 files changed, 401 insertions(+), 217 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
> delete mode 100644 arch/arm/include/asm/arch-stm32f7/rcc.h
> create mode 100644 arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
> rename drivers/clk/{clk_stm32f7.c => clk_stm32f.c} (56%)
> create mode 100644 include/stm32_rcc.h
>
^ permalink raw reply [flat|nested] 24+ messages in thread