* ✓ Fi.CI.BAT: success for drm/i915/execlists: Cache ELSP register offset
2017-12-07 20:45 [PATCH] drm/i915/execlists: Cache ELSP register offset Chris Wilson
@ 2017-12-07 21:04 ` Patchwork
2017-12-07 22:19 ` [PATCH] " Michel Thierry
` (4 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2017-12-07 21:04 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/execlists: Cache ELSP register offset
URL : https://patchwork.freedesktop.org/series/35054/
State : success
== Summary ==
Series 35054v1 drm/i915/execlists: Cache ELSP register offset
https://patchwork.freedesktop.org/api/1.0/series/35054/revisions/1/mbox/
Test debugfs_test:
Subgroup read_all_entries:
dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:436s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:381s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:524s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:281s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:507s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:506s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:485s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:470s
fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45
fi-gdg-551 total:288 pass:179 dwarn:1 dfail:0 fail:0 skip:108 time:271s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:538s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:371s
fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:259s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:392s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:474s
fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:449s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:483s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:524s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:481s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:532s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:583s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:457s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:546s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:562s
fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:515s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:498s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:448s
fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:549s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:420s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:609s
fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:627s
fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:491s
fb6aa7cd0d6bfa86efb7a87938733f1272414690 drm-tip: 2017y-12m-07d-17h-43m-29s UTC integration manifest
c38557249ae5 drm/i915/execlists: Cache ELSP register offset
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7443/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH] drm/i915/execlists: Cache ELSP register offset
2017-12-07 20:45 [PATCH] drm/i915/execlists: Cache ELSP register offset Chris Wilson
2017-12-07 21:04 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-12-07 22:19 ` Michel Thierry
2017-12-07 22:23 ` Chris Wilson
2017-12-07 22:24 ` [PATCH v2] " Chris Wilson
` (3 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Michel Thierry @ 2017-12-07 22:19 UTC (permalink / raw)
To: Chris Wilson, intel-gfx@lists.freedesktop.org
On 07/12/17 12:45, Chris Wilson wrote:
> Currently on every submission, we recalculate the ELSP register offset
> for the engine, after chasing the pointers to find the iomem base. Since
> this is fixed for the lifetime of the driver record the offset in the
> execlists struct.
>
> In practice the difference is negligible, it just happens to remove 27
> bytes of eyesore pointer dancing from next to the hottest instruction
> (which is itself due to stalling for a cache miss) in perf profiles of
> the execlists_submission_tasklet().
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++++
> 2 files changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 2a8160f603ab..93b5ce6307af 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -431,8 +431,7 @@ static inline void elsp_write(u64 desc, u32 __iomem *elsp)
> static void execlists_submit_ports(struct intel_engine_cs *engine)
> {
> struct execlist_port *port = engine->execlists.port;
> - u32 __iomem *elsp =
> - engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
> + u32 __iomem *elsp = engine->execlists.elsp;
> unsigned int n;
>
> for (n = execlists_num_ports(&engine->execlists); n--; ) {
Since you're moving this, probably it can now use engine->execlists.elsp
directly (as inject_preempt_context does), i.e.:
---
@@ -431,7 +431,6 @@ static inline void elsp_write(u64 desc, u32 __iomem
*elsp)
static void execlists_submit_ports(struct intel_engine_cs *engine)
{
struct execlist_port *port = engine->execlists.port;
- u32 __iomem *elsp = engine->execlists.elsp;
unsigned int n;
for (n = execlists_num_ports(&engine->execlists); n--; ) {
@@ -457,7 +456,7 @@ static void execlists_submit_ports(struct
intel_engine_cs *engine)
desc = 0;
}
- elsp_write(desc, elsp);
+ elsp_write(desc, engine->execlists.elsp);
}
execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
}
---
Anyway,
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
> @@ -496,8 +495,6 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
> {
> struct intel_context *ce =
> &engine->i915->preempt_context->engine[engine->id];
> - u32 __iomem *elsp =
> - engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
> unsigned int n;
>
> GEM_BUG_ON(engine->i915->preempt_context->hw_id != PREEMPT_ID);
> @@ -510,9 +507,9 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
>
> GEM_TRACE("\n");
> for (n = execlists_num_ports(&engine->execlists); --n; )
> - elsp_write(0, elsp);
> + elsp_write(0, engine->execlists.elsp);
>
> - elsp_write(ce->lrc_desc, elsp);
> + elsp_write(ce->lrc_desc, engine->execlists.elsp);
> execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
> }
>
> @@ -1509,6 +1506,9 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
> execlists->csb_head = -1;
> execlists->active = 0;
>
> + execlists->elsp =
> + dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));
> +
> /* After a GPU reset, we may have requests to replay */
> if (execlists->first)
> tasklet_schedule(&execlists->tasklet);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index c68ab3ead83c..183165b9b3fb 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -199,6 +199,11 @@ struct intel_engine_execlists {
> */
> bool no_priolist;
>
> + /**
> + * @elsp: the ExecList Submission Port register
> + */
> + u32 __iomem *elsp;
> +
> /**
> * @port: execlist port states
> *
> --
> 2.15.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH] drm/i915/execlists: Cache ELSP register offset
2017-12-07 22:19 ` [PATCH] " Michel Thierry
@ 2017-12-07 22:23 ` Chris Wilson
0 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2017-12-07 22:23 UTC (permalink / raw)
To: Michel Thierry, intel-gfx@lists.freedesktop.org
Quoting Michel Thierry (2017-12-07 22:19:05)
> On 07/12/17 12:45, Chris Wilson wrote:
> > Currently on every submission, we recalculate the ELSP register offset
> > for the engine, after chasing the pointers to find the iomem base. Since
> > this is fixed for the lifetime of the driver record the offset in the
> > execlists struct.
> >
> > In practice the difference is negligible, it just happens to remove 27
> > bytes of eyesore pointer dancing from next to the hottest instruction
> > (which is itself due to stalling for a cache miss) in perf profiles of
> > the execlists_submission_tasklet().
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_lrc.c | 12 ++++++------
> > drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++++
> > 2 files changed, 11 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index 2a8160f603ab..93b5ce6307af 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -431,8 +431,7 @@ static inline void elsp_write(u64 desc, u32 __iomem *elsp)
> > static void execlists_submit_ports(struct intel_engine_cs *engine)
> > {
> > struct execlist_port *port = engine->execlists.port;
> > - u32 __iomem *elsp =
> > - engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
> > + u32 __iomem *elsp = engine->execlists.elsp;
> > unsigned int n;
> >
> > for (n = execlists_num_ports(&engine->execlists); n--; ) {
>
> Since you're moving this, probably it can now use engine->execlists.elsp
> directly (as inject_preempt_context does), i.e.:
In fact, gcc prefers it. Odd that it generates different code at all, I
wonder what it is actually doing...
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2] drm/i915/execlists: Cache ELSP register offset
2017-12-07 20:45 [PATCH] drm/i915/execlists: Cache ELSP register offset Chris Wilson
2017-12-07 21:04 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-12-07 22:19 ` [PATCH] " Michel Thierry
@ 2017-12-07 22:24 ` Chris Wilson
2017-12-07 23:04 ` Rodrigo Vivi
2017-12-07 22:47 ` ✓ Fi.CI.BAT: success for drm/i915/execlists: Cache ELSP register offset (rev2) Patchwork
` (2 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Chris Wilson @ 2017-12-07 22:24 UTC (permalink / raw)
To: intel-gfx
Currently on every submission, we recalculate the ELSP register offset
for the engine, after chasing the pointers to find the iomem base. Since
this is fixed for the lifetime of the driver record the offset in the
execlists struct.
In practice the difference is negligible, it just happens to remove 27
bytes of eyesore pointer dancing from next to the hottest instruction
(which is itself due to stalling for a cache miss) in perf profiles of
the execlists_submission_tasklet().
v2: Trim off one more elsp local.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 13 ++++++-------
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++++
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2a8160f603ab..2e38fbfdf08f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -431,8 +431,6 @@ static inline void elsp_write(u64 desc, u32 __iomem *elsp)
static void execlists_submit_ports(struct intel_engine_cs *engine)
{
struct execlist_port *port = engine->execlists.port;
- u32 __iomem *elsp =
- engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
unsigned int n;
for (n = execlists_num_ports(&engine->execlists); n--; ) {
@@ -458,7 +456,7 @@ static void execlists_submit_ports(struct intel_engine_cs *engine)
desc = 0;
}
- elsp_write(desc, elsp);
+ elsp_write(desc, engine->execlists.elsp);
}
execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
}
@@ -496,8 +494,6 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
{
struct intel_context *ce =
&engine->i915->preempt_context->engine[engine->id];
- u32 __iomem *elsp =
- engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
unsigned int n;
GEM_BUG_ON(engine->i915->preempt_context->hw_id != PREEMPT_ID);
@@ -510,9 +506,9 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
GEM_TRACE("\n");
for (n = execlists_num_ports(&engine->execlists); --n; )
- elsp_write(0, elsp);
+ elsp_write(0, engine->execlists.elsp);
- elsp_write(ce->lrc_desc, elsp);
+ elsp_write(ce->lrc_desc, engine->execlists.elsp);
execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
}
@@ -1509,6 +1505,9 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
execlists->csb_head = -1;
execlists->active = 0;
+ execlists->elsp =
+ dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));
+
/* After a GPU reset, we may have requests to replay */
if (execlists->first)
tasklet_schedule(&execlists->tasklet);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index c68ab3ead83c..183165b9b3fb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -199,6 +199,11 @@ struct intel_engine_execlists {
*/
bool no_priolist;
+ /**
+ * @elsp: the ExecList Submission Port register
+ */
+ u32 __iomem *elsp;
+
/**
* @port: execlist port states
*
--
2.15.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v2] drm/i915/execlists: Cache ELSP register offset
2017-12-07 22:24 ` [PATCH v2] " Chris Wilson
@ 2017-12-07 23:04 ` Rodrigo Vivi
2017-12-07 23:11 ` Chris Wilson
2017-12-08 0:43 ` Chris Wilson
0 siblings, 2 replies; 11+ messages in thread
From: Rodrigo Vivi @ 2017-12-07 23:04 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Dec 07, 2017 at 10:24:34PM +0000, Chris Wilson wrote:
> Currently on every submission, we recalculate the ELSP register offset
> for the engine, after chasing the pointers to find the iomem base. Since
> this is fixed for the lifetime of the driver record the offset in the
> execlists struct.
>
> In practice the difference is negligible, it just happens to remove 27
> bytes of eyesore pointer dancing from next to the hottest instruction
> (which is itself due to stalling for a cache miss) in perf profiles of
> the execlists_submission_tasklet().
>
> v2: Trim off one more elsp local.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
would this be useful somehow on error state?
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 13 ++++++-------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++++
> 2 files changed, 11 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 2a8160f603ab..2e38fbfdf08f 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -431,8 +431,6 @@ static inline void elsp_write(u64 desc, u32 __iomem *elsp)
> static void execlists_submit_ports(struct intel_engine_cs *engine)
> {
> struct execlist_port *port = engine->execlists.port;
> - u32 __iomem *elsp =
> - engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
> unsigned int n;
>
> for (n = execlists_num_ports(&engine->execlists); n--; ) {
> @@ -458,7 +456,7 @@ static void execlists_submit_ports(struct intel_engine_cs *engine)
> desc = 0;
> }
>
> - elsp_write(desc, elsp);
> + elsp_write(desc, engine->execlists.elsp);
> }
> execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
> }
> @@ -496,8 +494,6 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
> {
> struct intel_context *ce =
> &engine->i915->preempt_context->engine[engine->id];
> - u32 __iomem *elsp =
> - engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
> unsigned int n;
>
> GEM_BUG_ON(engine->i915->preempt_context->hw_id != PREEMPT_ID);
> @@ -510,9 +506,9 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
>
> GEM_TRACE("\n");
> for (n = execlists_num_ports(&engine->execlists); --n; )
> - elsp_write(0, elsp);
> + elsp_write(0, engine->execlists.elsp);
>
> - elsp_write(ce->lrc_desc, elsp);
> + elsp_write(ce->lrc_desc, engine->execlists.elsp);
> execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
> }
>
> @@ -1509,6 +1505,9 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
> execlists->csb_head = -1;
> execlists->active = 0;
>
> + execlists->elsp =
> + dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));
> +
> /* After a GPU reset, we may have requests to replay */
> if (execlists->first)
> tasklet_schedule(&execlists->tasklet);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index c68ab3ead83c..183165b9b3fb 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -199,6 +199,11 @@ struct intel_engine_execlists {
> */
> bool no_priolist;
>
> + /**
> + * @elsp: the ExecList Submission Port register
> + */
> + u32 __iomem *elsp;
> +
> /**
> * @port: execlist port states
> *
> --
> 2.15.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2] drm/i915/execlists: Cache ELSP register offset
2017-12-07 23:04 ` Rodrigo Vivi
@ 2017-12-07 23:11 ` Chris Wilson
2017-12-08 0:43 ` Chris Wilson
1 sibling, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2017-12-07 23:11 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
Quoting Rodrigo Vivi (2017-12-07 23:04:13)
> On Thu, Dec 07, 2017 at 10:24:34PM +0000, Chris Wilson wrote:
> > Currently on every submission, we recalculate the ELSP register offset
> > for the engine, after chasing the pointers to find the iomem base. Since
> > this is fixed for the lifetime of the driver record the offset in the
> > execlists struct.
> >
> > In practice the difference is negligible, it just happens to remove 27
> > bytes of eyesore pointer dancing from next to the hottest instruction
> > (which is itself due to stalling for a cache miss) in perf profiles of
> > the execlists_submission_tasklet().
> >
> > v2: Trim off one more elsp local.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Reviewed-by: Michel Thierry <michel.thierry@intel.com>
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> would this be useful somehow on error state?
Nope, write-only register. We do how what we think is in ELSP, i.e. what
we last wrote to ELSP.
-Chris
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/i915/execlists: Cache ELSP register offset
2017-12-07 23:04 ` Rodrigo Vivi
2017-12-07 23:11 ` Chris Wilson
@ 2017-12-08 0:43 ` Chris Wilson
1 sibling, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2017-12-08 0:43 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
Quoting Rodrigo Vivi (2017-12-07 23:04:13)
> On Thu, Dec 07, 2017 at 10:24:34PM +0000, Chris Wilson wrote:
> > Currently on every submission, we recalculate the ELSP register offset
> > for the engine, after chasing the pointers to find the iomem base. Since
> > this is fixed for the lifetime of the driver record the offset in the
> > execlists struct.
> >
> > In practice the difference is negligible, it just happens to remove 27
> > bytes of eyesore pointer dancing from next to the hottest instruction
> > (which is itself due to stalling for a cache miss) in perf profiles of
> > the execlists_submission_tasklet().
> >
> > v2: Trim off one more elsp local.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Reviewed-by: Michel Thierry <michel.thierry@intel.com>
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Thanks for the reviews, applied.
-Chris
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^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/execlists: Cache ELSP register offset (rev2)
2017-12-07 20:45 [PATCH] drm/i915/execlists: Cache ELSP register offset Chris Wilson
` (2 preceding siblings ...)
2017-12-07 22:24 ` [PATCH v2] " Chris Wilson
@ 2017-12-07 22:47 ` Patchwork
2017-12-07 23:37 ` ✗ Fi.CI.IGT: warning for drm/i915/execlists: Cache ELSP register offset Patchwork
2017-12-08 1:22 ` ✗ Fi.CI.IGT: warning for drm/i915/execlists: Cache ELSP register offset (rev2) Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2017-12-07 22:47 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/execlists: Cache ELSP register offset (rev2)
URL : https://patchwork.freedesktop.org/series/35054/
State : success
== Summary ==
Series 35054v2 drm/i915/execlists: Cache ELSP register offset
https://patchwork.freedesktop.org/api/1.0/series/35054/revisions/2/mbox/
Test debugfs_test:
Subgroup read_all_entries:
dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:444s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:384s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:529s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:281s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:501s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:504s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:488s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:475s
fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45
fi-gdg-551 total:288 pass:179 dwarn:1 dfail:0 fail:0 skip:108 time:268s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:539s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:370s
fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:259s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:398s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:477s
fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:446s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:491s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:524s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:472s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:533s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:587s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:454s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:543s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:563s
fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:517s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:502s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:450s
fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:547s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:413s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:602s
fi-cnl-y total:249 pass:224 dwarn:0 dfail:0 fail:0 skip:24
fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:490s
fb6aa7cd0d6bfa86efb7a87938733f1272414690 drm-tip: 2017y-12m-07d-17h-43m-29s UTC integration manifest
4eacbdb08b51 drm/i915/execlists: Cache ELSP register offset
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7446/
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^ permalink raw reply [flat|nested] 11+ messages in thread* ✗ Fi.CI.IGT: warning for drm/i915/execlists: Cache ELSP register offset
2017-12-07 20:45 [PATCH] drm/i915/execlists: Cache ELSP register offset Chris Wilson
` (3 preceding siblings ...)
2017-12-07 22:47 ` ✓ Fi.CI.BAT: success for drm/i915/execlists: Cache ELSP register offset (rev2) Patchwork
@ 2017-12-07 23:37 ` Patchwork
2017-12-08 1:22 ` ✗ Fi.CI.IGT: warning for drm/i915/execlists: Cache ELSP register offset (rev2) Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2017-12-07 23:37 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/execlists: Cache ELSP register offset
URL : https://patchwork.freedesktop.org/series/35054/
State : warning
== Summary ==
Test kms_flip:
Subgroup flip-vs-modeset-vs-hang:
pass -> DMESG-WARN (shard-snb)
Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
pass -> INCOMPLETE (shard-hsw) fdo#103540
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b:
incomplete -> PASS (shard-hsw)
Test drv_module_reload:
Subgroup basic-reload:
pass -> DMESG-WARN (shard-snb) fdo#102848
pass -> DMESG-WARN (shard-hsw) fdo#102707
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail -> PASS (shard-snb) fdo#101623
Test pm_rc6_residency:
Subgroup rc6-accuracy:
pass -> SKIP (shard-snb)
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102848 https://bugs.freedesktop.org/show_bug.cgi?id=102848
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
shard-hsw total:2610 pass:1491 dwarn:2 dfail:0 fail:9 skip:1107 time:9088s
shard-snb total:2679 pass:1305 dwarn:3 dfail:0 fail:12 skip:1359 time:8101s
Blacklisted hosts:
shard-apl total:2679 pass:1679 dwarn:1 dfail:0 fail:22 skip:977 time:13725s
shard-kbl total:2620 pass:1760 dwarn:2 dfail:1 fail:24 skip:832 time:10744s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7443/shards.html
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^ permalink raw reply [flat|nested] 11+ messages in thread* ✗ Fi.CI.IGT: warning for drm/i915/execlists: Cache ELSP register offset (rev2)
2017-12-07 20:45 [PATCH] drm/i915/execlists: Cache ELSP register offset Chris Wilson
` (4 preceding siblings ...)
2017-12-07 23:37 ` ✗ Fi.CI.IGT: warning for drm/i915/execlists: Cache ELSP register offset Patchwork
@ 2017-12-08 1:22 ` Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2017-12-08 1:22 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/execlists: Cache ELSP register offset (rev2)
URL : https://patchwork.freedesktop.org/series/35054/
State : warning
== Summary ==
Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
pass -> SKIP (shard-snb) fdo#102365
Test kms_flip:
Subgroup flip-vs-panning:
incomplete -> PASS (shard-hsw)
Test drv_module_reload:
Subgroup basic-reload:
pass -> DMESG-WARN (shard-hsw) fdo#102707
Test pm_rc6_residency:
Subgroup rc6-accuracy:
pass -> SKIP (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
fail -> PASS (shard-snb) fdo#101623
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b:
incomplete -> PASS (shard-hsw)
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
shard-hsw total:2679 pass:1535 dwarn:2 dfail:0 fail:10 skip:1132 time:9489s
shard-snb total:2679 pass:1306 dwarn:1 dfail:0 fail:12 skip:1360 time:8067s
Blacklisted hosts:
shard-apl total:2679 pass:1677 dwarn:1 dfail:0 fail:24 skip:977 time:13774s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7446/shards.html
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^ permalink raw reply [flat|nested] 11+ messages in thread