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From: Miquel RAYNAL <miquel.raynal@free-electrons.com>
To: Baruch Siach <baruch@tkos.co.il>
Cc: Zhang Rui <rui.zhang@intel.com>,
	Eduardo Valentin <edubezval@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
	Gregory Clement <gregory.clement@free-electrons.com>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>,
	linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
	Antoine Tenart <antoine.tenart@free-electrons.com>,
	Nadav Haklai <nadavh@marvell.com>,
	David Sniatkiwicz <davidsn@marvell.com>
Subject: Re: [PATCH v4 04/12] thermal: armada: Clarify control registers accesses
Date: Tue, 19 Dec 2017 09:23:45 +0100	[thread overview]
Message-ID: <20171219092345.470fd427@xps13> (raw)
In-Reply-To: <20171219081941.utke7dh5bmmlub6h@sapphire.tkos.co.il>

Hi Baruch,

On Tue, 19 Dec 2017 10:19:41 +0200
Baruch Siach <baruch@tkos.co.il> wrote:

> Hi Miquèl,
> 
> On Tue, Dec 19, 2017 at 09:08:14AM +0100, Miquel RAYNAL wrote:
> > On Tue, 19 Dec 2017 07:51:54 +0200
> > Baruch Siach <baruch@tkos.co.il> wrote:  
> > > On Tue, Dec 19, 2017 at 01:32:33AM +0100, Miquel RAYNAL wrote:  
> > > > On Mon, 18 Dec 2017 22:35:42 +0200
> > > > Baruch Siach <baruch@tkos.co.il> wrote:    
> > > > > On Mon, Dec 18, 2017 at 03:36:35PM +0100, Miquel Raynal
> > > > > wrote:    
> > > > > > Bindings were incomplete for a long time by only exposing
> > > > > > one of the two available control registers. To ease the
> > > > > > migration to the full bindings (already in use for the
> > > > > > Armada 375 SoC), rename the pointers for clarification.
> > > > > > This way, it will only be needed to add another pointer to
> > > > > > access the other control register when the time comes.
> > > > > > 
> > > > > > This avoids dangerous situations where the offset 0 of the
> > > > > > control area can be either one register or the other
> > > > > > depending on the bindings used. After this change, device
> > > > > > trees of other SoCs could be migrated to the "full"
> > > > > > bindings if they may benefit from features from the
> > > > > > unaccessible register, without any change in the driver.
> > > > > > 
> > > > > > Signed-off-by: Miquel Raynal
> > > > > > <miquel.raynal@free-electrons.com> Reviewed-by: Gregory
> > > > > > CLEMENT <gregory.clement@free-electrons.com> ---      
> > > > > 
> > > > > [...]
> > > > >     
> > > > > > +	/*
> > > > > > +	 * Legacy DT bindings only described "control1"
> > > > > > register (also referred
> > > > > > +	 * as "control MSB" on old documentation). New
> > > > > > bindings cover
> > > > > > +	 * "control0/control LSB" and "control1/control
> > > > > > MSB" registers within
> > > > > > +	 * the same resource, which is then of size 8
> > > > > > instead of 4.
> > > > > > +	 */
> > > > > > +	if (resource_size(res) == LEGACY_CONTROL_MEM_LEN) {
> > > > > > +		/* ->control0 unavailable in this
> > > > > > configuration */
> > > > > > +		priv->control1 = control +
> > > > > > LEGACY_CONTROL1_OFFSET;
> > > > > > +	} else {
> > > > > > +		priv->control0 = control + CONTROL0_OFFSET;
> > > > > > +		priv->control1 = control + CONTROL1_OFFSET;
> > > > > > +	}      
> > > > > 
> > > > > The needs_control0 field that you mentioned in the cover page
> > > > > is missing here.    
> > > > 
> > > > Yes, at this point nobody actually *needs* control0 so the
> > > > limitation is added with the patch that introduce ap806 support
> > > > as it is the first compatible that needs both control0 and
> > > > control1 to work correctly. Does this bother you?    
> > > 
> > > No. It is just that we agreed to have a verification here that the
> > > size of the control registers resource matches the binding. I
> > > thought that the needs_control0 field that you mention in the
> > > cover page is meant to implement that.  
> > 
> > That is absolutely right, but at this point in the series, the
> > supported compatible strings are
> > "marvell,armada[370|375|38x|xp]-thermal". All of them can use both
> > bindings so I don't see the point to have a needs_control0 field in
> > this patch. It is introduced in the next patch that adds support
> > for ap806 by only supporting the new bindings though.  
> 
> OK. Makes sense.
> 
> > > necessary. It would just make sure that no one introduces a DT
> > > with the wrong resource size.  
> > 
> > Not sure I understand what exactly you wanna check, can you
> > give me an example?  
> 
> I wrote that before it occurred to me that we can use the control
> registers size the distinguish between the old binding and the new
> one.
> 
> I still think it would be nice to add needs_control0=true to
> armada375_data, for consistency with the ap806 and cp110.

Oh that is right, I forgot about that. I will add it and move the
need_control0 boolean to this patch.

Thank you,
Miquèl

> 
> baruch
> 



-- 
Miquel Raynal, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

WARNING: multiple messages have this Message-ID (diff)
From: miquel.raynal@free-electrons.com (Miquel RAYNAL)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 04/12] thermal: armada: Clarify control registers accesses
Date: Tue, 19 Dec 2017 09:23:45 +0100	[thread overview]
Message-ID: <20171219092345.470fd427@xps13> (raw)
In-Reply-To: <20171219081941.utke7dh5bmmlub6h@sapphire.tkos.co.il>

Hi Baruch,

On Tue, 19 Dec 2017 10:19:41 +0200
Baruch Siach <baruch@tkos.co.il> wrote:

> Hi Miqu?l,
> 
> On Tue, Dec 19, 2017 at 09:08:14AM +0100, Miquel RAYNAL wrote:
> > On Tue, 19 Dec 2017 07:51:54 +0200
> > Baruch Siach <baruch@tkos.co.il> wrote:  
> > > On Tue, Dec 19, 2017 at 01:32:33AM +0100, Miquel RAYNAL wrote:  
> > > > On Mon, 18 Dec 2017 22:35:42 +0200
> > > > Baruch Siach <baruch@tkos.co.il> wrote:    
> > > > > On Mon, Dec 18, 2017 at 03:36:35PM +0100, Miquel Raynal
> > > > > wrote:    
> > > > > > Bindings were incomplete for a long time by only exposing
> > > > > > one of the two available control registers. To ease the
> > > > > > migration to the full bindings (already in use for the
> > > > > > Armada 375 SoC), rename the pointers for clarification.
> > > > > > This way, it will only be needed to add another pointer to
> > > > > > access the other control register when the time comes.
> > > > > > 
> > > > > > This avoids dangerous situations where the offset 0 of the
> > > > > > control area can be either one register or the other
> > > > > > depending on the bindings used. After this change, device
> > > > > > trees of other SoCs could be migrated to the "full"
> > > > > > bindings if they may benefit from features from the
> > > > > > unaccessible register, without any change in the driver.
> > > > > > 
> > > > > > Signed-off-by: Miquel Raynal
> > > > > > <miquel.raynal@free-electrons.com> Reviewed-by: Gregory
> > > > > > CLEMENT <gregory.clement@free-electrons.com> ---      
> > > > > 
> > > > > [...]
> > > > >     
> > > > > > +	/*
> > > > > > +	 * Legacy DT bindings only described "control1"
> > > > > > register (also referred
> > > > > > +	 * as "control MSB" on old documentation). New
> > > > > > bindings cover
> > > > > > +	 * "control0/control LSB" and "control1/control
> > > > > > MSB" registers within
> > > > > > +	 * the same resource, which is then of size 8
> > > > > > instead of 4.
> > > > > > +	 */
> > > > > > +	if (resource_size(res) == LEGACY_CONTROL_MEM_LEN) {
> > > > > > +		/* ->control0 unavailable in this
> > > > > > configuration */
> > > > > > +		priv->control1 = control +
> > > > > > LEGACY_CONTROL1_OFFSET;
> > > > > > +	} else {
> > > > > > +		priv->control0 = control + CONTROL0_OFFSET;
> > > > > > +		priv->control1 = control + CONTROL1_OFFSET;
> > > > > > +	}      
> > > > > 
> > > > > The needs_control0 field that you mentioned in the cover page
> > > > > is missing here.    
> > > > 
> > > > Yes, at this point nobody actually *needs* control0 so the
> > > > limitation is added with the patch that introduce ap806 support
> > > > as it is the first compatible that needs both control0 and
> > > > control1 to work correctly. Does this bother you?    
> > > 
> > > No. It is just that we agreed to have a verification here that the
> > > size of the control registers resource matches the binding. I
> > > thought that the needs_control0 field that you mention in the
> > > cover page is meant to implement that.  
> > 
> > That is absolutely right, but at this point in the series, the
> > supported compatible strings are
> > "marvell,armada[370|375|38x|xp]-thermal". All of them can use both
> > bindings so I don't see the point to have a needs_control0 field in
> > this patch. It is introduced in the next patch that adds support
> > for ap806 by only supporting the new bindings though.  
> 
> OK. Makes sense.
> 
> > > necessary. It would just make sure that no one introduces a DT
> > > with the wrong resource size.  
> > 
> > Not sure I understand what exactly you wanna check, can you
> > give me an example?  
> 
> I wrote that before it occurred to me that we can use the control
> registers size the distinguish between the old binding and the new
> one.
> 
> I still think it would be nice to add needs_control0=true to
> armada375_data, for consistency with the ap806 and cp110.

Oh that is right, I forgot about that. I will add it and move the
need_control0 boolean to this patch.

Thank you,
Miqu?l

> 
> baruch
> 



-- 
Miquel Raynal, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

  reply	other threads:[~2017-12-19  8:23 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-18 14:36 [PATCH v4 00/12] Armada thermal: improvements and A7K/A8K SoCs support Miquel Raynal
2017-12-18 14:36 ` Miquel Raynal
2017-12-18 14:36 ` [PATCH v4 01/12] dt-bindings: thermal: Describe Armada AP806 and CP110 Miquel Raynal
2017-12-18 14:36   ` Miquel Raynal
     [not found]   ` <20171218143643.7714-2-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 20:33     ` Baruch Siach
2017-12-18 20:33       ` Baruch Siach
2017-12-19  0:43       ` Miquel RAYNAL
2017-12-19  0:43         ` Miquel RAYNAL
2017-12-19  6:09         ` Baruch Siach
2017-12-19  6:09           ` Baruch Siach
     [not found]           ` <20171219060918.nr4ojwpmqf6ju6od-MwjkAAnuF3khR1HGirfZ1z4kX+cae0hd@public.gmane.org>
2017-12-19  7:44             ` Miquel RAYNAL
2017-12-19  7:44               ` Miquel RAYNAL
2017-12-18 14:36 ` [PATCH v4 02/12] thermal: armada: Use msleep for long delays Miquel Raynal
2017-12-18 14:36   ` Miquel Raynal
2017-12-18 14:36 ` [PATCH v4 04/12] thermal: armada: Clarify control registers accesses Miquel Raynal
2017-12-18 14:36   ` Miquel Raynal
     [not found]   ` <20171218143643.7714-5-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 20:35     ` Baruch Siach
2017-12-18 20:35       ` Baruch Siach
2017-12-19  0:32       ` Miquel RAYNAL
2017-12-19  0:32         ` Miquel RAYNAL
2017-12-19  5:51         ` Baruch Siach
2017-12-19  5:51           ` Baruch Siach
     [not found]           ` <20171219055154.f23leaob3zndmmqo-MwjkAAnuF3khR1HGirfZ1z4kX+cae0hd@public.gmane.org>
2017-12-19  8:08             ` Miquel RAYNAL
2017-12-19  8:08               ` Miquel RAYNAL
2017-12-19  8:19               ` Baruch Siach
2017-12-19  8:19                 ` Baruch Siach
2017-12-19  8:23                 ` Miquel RAYNAL [this message]
2017-12-19  8:23                   ` Miquel RAYNAL
2017-12-18 14:36 ` [PATCH v4 09/12] thermal: armada: Change sensors trim default value Miquel Raynal
2017-12-18 14:36   ` Miquel Raynal
     [not found]   ` <20171218143643.7714-10-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 16:08     ` Gregory CLEMENT
2017-12-18 16:08       ` Gregory CLEMENT
     [not found] ` <20171218143643.7714-1-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 14:36   ` [PATCH v4 03/12] thermal: armada: Simplify the check of the validity bit Miquel Raynal
2017-12-18 14:36     ` Miquel Raynal
2017-12-18 14:36   ` [PATCH v4 05/12] thermal: armada: Use real status register name Miquel Raynal
2017-12-18 14:36     ` Miquel Raynal
     [not found]     ` <20171218143643.7714-6-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 15:58       ` Gregory CLEMENT
2017-12-18 15:58         ` Gregory CLEMENT
2017-12-18 14:36   ` [PATCH v4 06/12] thermal: armada: Add support for Armada AP806 Miquel Raynal
2017-12-18 14:36     ` Miquel Raynal
     [not found]     ` <20171218143643.7714-7-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 16:05       ` Gregory CLEMENT
2017-12-18 16:05         ` Gregory CLEMENT
     [not found]         ` <87y3m0hvik.fsf-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-19  0:27           ` Miquel RAYNAL
2017-12-19  0:27             ` Miquel RAYNAL
2017-12-18 14:36   ` [PATCH v4 07/12] thermal: armada: Add support for Armada CP110 Miquel Raynal
2017-12-18 14:36     ` Miquel Raynal
     [not found]     ` <20171218143643.7714-8-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 16:07       ` Gregory CLEMENT
2017-12-18 16:07         ` Gregory CLEMENT
2017-12-18 14:36   ` [PATCH v4 08/12] thermal: armada: Update Kconfig and module description Miquel Raynal
2017-12-18 14:36     ` Miquel Raynal
     [not found]     ` <20171218143643.7714-9-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 16:07       ` Gregory CLEMENT
2017-12-18 16:07         ` Gregory CLEMENT
2017-12-18 14:36   ` [PATCH v4 10/12] thermal: armada: Wait sensors validity before exiting the init callback Miquel Raynal
2017-12-18 14:36     ` Miquel Raynal
2017-12-18 16:12     ` Gregory CLEMENT
2017-12-18 16:12       ` Gregory CLEMENT
2017-12-18 14:36   ` [PATCH v4 11/12] thermal: armada: Give meaningful names to the thermal zones Miquel Raynal
2017-12-18 14:36     ` Miquel Raynal
2017-12-18 16:12     ` Gregory CLEMENT
2017-12-18 16:12       ` Gregory CLEMENT
2017-12-18 14:36   ` [PATCH v4 12/12] ARM64: dts: marvell: Add thermal support for A7K/A8K Miquel Raynal
2017-12-18 14:36     ` Miquel Raynal
2017-12-18 16:13     ` Gregory CLEMENT
2017-12-18 16:13       ` Gregory CLEMENT

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