From: Stephen Boyd <sboyd@codeaurora.org>
To: Joel Stanley <joel@jms.id.au>
Cc: Lee Jones <lee.jones@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Andrew Jeffery <andrew@aj.id.au>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Jeremy Kerr <jk@ozlabs.org>, Rick Altherr <raltherr@google.com>,
Ryan Chen <ryan_chen@aspeedtech.com>,
Arnd Bergmann <arnd@arndb.de>
Subject: Re: [PATCH v7 4/5] clk: aspeed: Register gated clocks
Date: Tue, 2 Jan 2018 17:47:03 -0800 [thread overview]
Message-ID: <20180103014703.GS7997@codeaurora.org> (raw)
In-Reply-To: <20171222024522.10362-5-joel@jms.id.au>
On 12/22, Joel Stanley wrote:
> The majority of the clocks in the system are gates paired with a reset
> controller that holds the IP in reset.
>
> This borrows from clk_hw_register_gate, but registers two 'gates', one
> to control the clock enable register and the other to control the reset
> IP. This allows us to enforce the ordering:
>
> 1. Place IP in reset
> 2. Enable clock
> 3. Delay
> 4. Release reset
>
> There are some gates that do not have an associated reset; these are
> handled by using -1 as the index for the reset.
>
> Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 4/5] clk: aspeed: Register gated clocks
Date: Tue, 2 Jan 2018 17:47:03 -0800 [thread overview]
Message-ID: <20180103014703.GS7997@codeaurora.org> (raw)
In-Reply-To: <20171222024522.10362-5-joel@jms.id.au>
On 12/22, Joel Stanley wrote:
> The majority of the clocks in the system are gates paired with a reset
> controller that holds the IP in reset.
>
> This borrows from clk_hw_register_gate, but registers two 'gates', one
> to control the clock enable register and the other to control the reset
> IP. This allows us to enforce the ordering:
>
> 1. Place IP in reset
> 2. Enable clock
> 3. Delay
> 4. Release reset
>
> There are some gates that do not have an associated reset; these are
> handled by using -1 as the index for the reset.
>
> Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2018-01-03 1:47 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-22 2:45 [PATCH v7 0/5] clk: Add Aspeed clock driver Joel Stanley
2017-12-22 2:45 ` Joel Stanley
2017-12-22 2:45 ` [PATCH v7 1/5] clk: Add clock driver for ASPEED BMC SoCs Joel Stanley
2017-12-22 2:45 ` Joel Stanley
2018-01-02 5:48 ` Benjamin Herrenschmidt
2018-01-02 5:48 ` Benjamin Herrenschmidt
2018-01-03 1:46 ` Stephen Boyd
2018-01-03 1:46 ` Stephen Boyd
2017-12-22 2:45 ` [PATCH v7 2/5] clk: aspeed: Register core clocks Joel Stanley
2017-12-22 2:45 ` Joel Stanley
2018-01-02 5:49 ` Benjamin Herrenschmidt
2018-01-02 5:49 ` Benjamin Herrenschmidt
2018-01-03 1:46 ` Stephen Boyd
2018-01-03 1:46 ` Stephen Boyd
2017-12-22 2:45 ` [PATCH v7 3/5] clk: aspeed: Add platform driver and register PLLs Joel Stanley
2017-12-22 2:45 ` Joel Stanley
2018-01-02 5:49 ` Benjamin Herrenschmidt
2018-01-02 5:49 ` Benjamin Herrenschmidt
2018-01-03 1:47 ` Stephen Boyd
2018-01-03 1:47 ` Stephen Boyd
2017-12-22 2:45 ` [PATCH v7 4/5] clk: aspeed: Register gated clocks Joel Stanley
2017-12-22 2:45 ` Joel Stanley
2018-01-02 5:50 ` Benjamin Herrenschmidt
2018-01-02 5:50 ` Benjamin Herrenschmidt
2018-01-03 1:47 ` Stephen Boyd [this message]
2018-01-03 1:47 ` Stephen Boyd
2017-12-22 2:45 ` [PATCH v7 5/5] clk: aspeed: Add reset controller Joel Stanley
2017-12-22 2:45 ` Joel Stanley
2018-01-02 5:50 ` Benjamin Herrenschmidt
2018-01-02 5:50 ` Benjamin Herrenschmidt
2018-01-03 1:47 ` Stephen Boyd
2018-01-03 1:47 ` Stephen Boyd
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