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From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Cc: linux-pci@vger.kernel.org, bhelgaas@google.com,
	marc.zyngier@arm.com, robh@kernel.org,
	devicetree@vger.kernel.org, mingkai.hu@nxp.com,
	peter.newton@nxp.com, minghuan.lian@nxp.com,
	rajesh.raina@nxp.com, rajan.kapoor@nxp.com,
	prabhjot.singh@nxp.com
Subject: Re: [PATCH v5 2/3] PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver
Date: Fri, 5 Jan 2018 14:01:02 +0000	[thread overview]
Message-ID: <20180105140102.GA24933@red-moon> (raw)
In-Reply-To: <20171220170307.GC1709@red-moon>

On Wed, Dec 20, 2017 at 05:03:07PM +0000, Lorenzo Pieralisi wrote:

[...]

> > +static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
> > +{
> > +	struct device *dev = &pcie->pdev->dev;
> > +	struct device_node *node = dev->of_node;
> > +	int ret;
> 
> ret is unused
> 
> > +	/* setup INTx */
> > +	pcie->intx_domain = irq_domain_add_linear(node,
> > +				PCI_NUM_INTX + 1, &intx_domain_ops, pcie);
> 
> You should use PCI_NUM_INTX and add pci_irqd_intx_xlate() as the
> domain ops .xlate.

Actually that's not quite correct - so scrap this. The point here is,
the PCI host controller interrupt domain has to have 4 hwirqs (this
is a pseudo interrupt controller - a multiplexer) and it
is through DT interrupt-map that INTx pins (1-4) can be mapped to the
"PCI interrupt controller hwirq inputs" that we consider numbered
from 0 to 3.

It is not that clean-cut but IMO it is the DT interrupt mapping that
should carry out the translation.

See for instance:

arch/arm64/boot/dts/marvell/armada-37xx.dtsi

This requires DT/irqchip maintainers acknowledgement before proceeding.

Lorenzo

WARNING: multiple messages have this Message-ID (diff)
From: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
To: Subrahmanya Lingappa
	<l.subrahmanya-DTHOJn6Rh8lhmhkoCovsdw@public.gmane.org>
Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
	marc.zyngier-5wv7dgnIgG8@public.gmane.org,
	robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	mingkai.hu-3arQi8VN3Tc@public.gmane.org,
	peter.newton-3arQi8VN3Tc@public.gmane.org,
	minghuan.lian-3arQi8VN3Tc@public.gmane.org,
	rajesh.raina-3arQi8VN3Tc@public.gmane.org,
	rajan.kapoor-3arQi8VN3Tc@public.gmane.org,
	prabhjot.singh-3arQi8VN3Tc@public.gmane.org
Subject: Re: [PATCH v5 2/3] PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver
Date: Fri, 5 Jan 2018 14:01:02 +0000	[thread overview]
Message-ID: <20180105140102.GA24933@red-moon> (raw)
In-Reply-To: <20171220170307.GC1709@red-moon>

On Wed, Dec 20, 2017 at 05:03:07PM +0000, Lorenzo Pieralisi wrote:

[...]

> > +static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
> > +{
> > +	struct device *dev = &pcie->pdev->dev;
> > +	struct device_node *node = dev->of_node;
> > +	int ret;
> 
> ret is unused
> 
> > +	/* setup INTx */
> > +	pcie->intx_domain = irq_domain_add_linear(node,
> > +				PCI_NUM_INTX + 1, &intx_domain_ops, pcie);
> 
> You should use PCI_NUM_INTX and add pci_irqd_intx_xlate() as the
> domain ops .xlate.

Actually that's not quite correct - so scrap this. The point here is,
the PCI host controller interrupt domain has to have 4 hwirqs (this
is a pseudo interrupt controller - a multiplexer) and it
is through DT interrupt-map that INTx pins (1-4) can be mapped to the
"PCI interrupt controller hwirq inputs" that we consider numbered
from 0 to 3.

It is not that clean-cut but IMO it is the DT interrupt mapping that
should carry out the translation.

See for instance:

arch/arm64/boot/dts/marvell/armada-37xx.dtsi

This requires DT/irqchip maintainers acknowledgement before proceeding.

Lorenzo
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  parent reply	other threads:[~2018-01-05 14:00 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-13 16:08 [PATCH v5 2/3] PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver Subrahmanya Lingappa
2017-12-13 16:08 ` Subrahmanya Lingappa
2017-12-20 17:03 ` Lorenzo Pieralisi
2017-12-20 17:03   ` Lorenzo Pieralisi
2017-12-22  7:59   ` Subrahmanya Lingappa
2018-01-02 14:13     ` Lorenzo Pieralisi
2018-01-05  9:52       ` Subrahmanya Lingappa
2018-01-05 14:01   ` Lorenzo Pieralisi [this message]
2018-01-05 14:01     ` Lorenzo Pieralisi

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