From: Christoph Hellwig <hch@lst.de>
To: Michael Clark <mjc@sifive.com>
Cc: qemu-devel@nongnu.org,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
RISC-V Patches <patches+subscribe@groups.riscv.org>,
Palmer Dabbelt <palmer@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Subject: Re: [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2
Date: Thu, 11 Jan 2018 08:58:12 +0100 [thread overview]
Message-ID: <20180111075812.GA32651@lst.de> (raw)
In-Reply-To: <1515628000-93285-1-git-send-email-mjc@sifive.com>
On Wed, Jan 10, 2018 at 03:46:19PM -0800, Michael Clark wrote:
> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
Same question as for V2: Why do you want to add code for an obsolete
version of the privileged ISA spec? (which as far as I can tell
can't even be found online).
next prev parent reply other threads:[~2018-01-11 7:58 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-10 23:46 [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2 Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 01/21] RISC-V Maintainers Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 02/21] RISC-V ELF Machine Definition Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 03/21] RISC-V CPU Core Definition Michael Clark
2018-01-15 13:44 ` Igor Mammedov
2018-01-24 18:21 ` Michael Clark
2018-01-29 15:37 ` Igor Mammedov
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 04/21] RISC-V Disassembler Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 05/21] RISC-V CPU Helpers Michael Clark
2018-01-11 8:08 ` Christoph Hellwig
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 06/21] RISC-V FPU Support Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 07/21] RISC-V GDB Stub Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 08/21] RISC-V TCG Code Generation Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 09/21] RISC-V Physical Memory Protection Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 10/21] RISC-V Linux User Emulation Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 11/21] RISC-V HTIF Console Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 12/21] RISC-V HART Array Michael Clark
2018-01-15 13:19 ` Igor Mammedov
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 13/21] SiFive RISC-V CLINT Block Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 14/21] SiFive RISC-V PLIC Block Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 15/21] RISC-V Spike Machines Michael Clark
2018-01-15 13:27 ` Igor Mammedov
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 16/21] RISC-V VirtIO Machine Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 17/21] SiFive RISC-V UART Device Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 18/21] SiFive RISC-V PRCI Block Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 19/21] SiFive Freedom E300 RISC-V Machine Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 20/21] SiFive Freedom U500 " Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 21/21] RISC-V Build Infrastructure Michael Clark
2018-01-11 0:05 ` [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2 Michael Clark
2018-01-11 0:46 ` no-reply
2018-01-11 7:58 ` Christoph Hellwig [this message]
2018-01-11 18:24 ` Michael Clark
2018-01-12 8:09 ` Christoph Hellwig
2018-01-12 19:50 ` Palmer Dabbelt
2018-01-11 19:16 ` Palmer Dabbelt
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