From: Christoph Hellwig <hch@lst.de>
To: Michael Clark <mjc@sifive.com>
Cc: Christoph Hellwig <hch@lst.de>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>,
RISC-V Patches <patches+subscribe@groups.riscv.org>,
qemu-devel@nongnu.org,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Subject: Re: [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2
Date: Fri, 12 Jan 2018 09:09:16 +0100 [thread overview]
Message-ID: <20180112080916.GA23324@lst.de> (raw)
In-Reply-To: <CAHNT7Ns+ye2djyqKqr2VmHkjgTLxqkkr6=JKL2B7HvnQm3xRGQ@mail.gmail.com>
On Fri, Jan 12, 2018 at 07:24:54AM +1300, Michael Clark wrote:
> I'm going to be restoring branches for bbl and riscv-linux that work again
> priv 1.9.1. There are still other emulators and RTL that support priv1.9.1.
> Folk will have silicon against different versions of spec going forward.
> Likewise going forward we are still going to need to support v1.10 behavior
> when v1.11 is published. i.e. priv v1.10 mode is going to have to hide any
> additions made in priv v1.11. I use priv v1.9.1 during my QEMU testing.
> Hopefully, future changes are additive vs breaking...
That was the plan for 1.10+. And I thought that was because 1.10
is what people actually started implementing for real, but based on
the comment from Palmer that is not actually true. Sigh..
I guess at least for Linux we'd then want to make sure 1.9.1 support
is in mainline as well, probably based off a config option.
And if someone has a a good contact to the RISC-V website admins
it would be very helpful to restore a link to the specification as well
so that things other than the direct link work.
next prev parent reply other threads:[~2018-01-12 8:09 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-10 23:46 [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2 Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 01/21] RISC-V Maintainers Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 02/21] RISC-V ELF Machine Definition Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 03/21] RISC-V CPU Core Definition Michael Clark
2018-01-15 13:44 ` Igor Mammedov
2018-01-24 18:21 ` Michael Clark
2018-01-29 15:37 ` Igor Mammedov
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 04/21] RISC-V Disassembler Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 05/21] RISC-V CPU Helpers Michael Clark
2018-01-11 8:08 ` Christoph Hellwig
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 06/21] RISC-V FPU Support Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 07/21] RISC-V GDB Stub Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 08/21] RISC-V TCG Code Generation Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 09/21] RISC-V Physical Memory Protection Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 10/21] RISC-V Linux User Emulation Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 11/21] RISC-V HTIF Console Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 12/21] RISC-V HART Array Michael Clark
2018-01-15 13:19 ` Igor Mammedov
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 13/21] SiFive RISC-V CLINT Block Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 14/21] SiFive RISC-V PLIC Block Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 15/21] RISC-V Spike Machines Michael Clark
2018-01-15 13:27 ` Igor Mammedov
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 16/21] RISC-V VirtIO Machine Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 17/21] SiFive RISC-V UART Device Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 18/21] SiFive RISC-V PRCI Block Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 19/21] SiFive Freedom E300 RISC-V Machine Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 20/21] SiFive Freedom U500 " Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 21/21] RISC-V Build Infrastructure Michael Clark
2018-01-11 0:05 ` [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2 Michael Clark
2018-01-11 0:46 ` no-reply
2018-01-11 7:58 ` Christoph Hellwig
2018-01-11 18:24 ` Michael Clark
2018-01-12 8:09 ` Christoph Hellwig [this message]
2018-01-12 19:50 ` Palmer Dabbelt
2018-01-11 19:16 ` Palmer Dabbelt
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