[PATCH 0/4] drm/msm/dsi: Add DSI 10nm PLL/PHY drivers

[Archit Taneja <architt@codeaurora.org>]

Add the 10nm DSI PHY/PLL drivers. This will be used on the SDM845 SoC.
Most of the code is based on the corresponding downstream PLL [1] and
PHY [2] drivers.

The PHY driver has a few TODOs which would be resolved in future
patches.

[1] https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c?h=msm-4.9
[2] https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v3_0.c?h=msm-4.9

Archit Taneja (4):
  drm/msm/dsi: Update generated headers for 10nm PLL/PHY
  drm/msm/dsi: Add skeleton 10nm PHY/PLL code
  drm/msm/dsi: Populate PLL 10nm clock ops
  drm/msm/dsi: Populate the 10nm PHY funcs

 drivers/gpu/drm/msm/Kconfig                |   7 +
 drivers/gpu/drm/msm/Makefile               |   2 +
 drivers/gpu/drm/msm/dsi/dsi.h              |   1 +
 drivers/gpu/drm/msm/dsi/dsi.xml.h          | 187 ++++++-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c      |   4 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h      |   1 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 251 +++++++++
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c      |   3 +
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h      |   9 +
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 822 +++++++++++++++++++++++++++++
 10 files changed, 1274 insertions(+), 13 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
 create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c

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