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From: Archit Taneja <architt@codeaurora.org>
To: robdclark@gmail.com
Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	latkinso@codeaurora.org, dri-devel@lists.freedesktop.org,
	sibis@codeaurora.org
Subject: [PATCH 6/7] dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHY
Date: Wed, 17 Jan 2018 15:04:47 +0530	[thread overview]
Message-ID: <20180117093448.4102-7-architt@codeaurora.org> (raw)
In-Reply-To: <20180117093448.4102-1-architt@codeaurora.org>

Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096).
From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required,
but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names
each PHY revision needs.

Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
 Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
index 9c3ad6bbb9f0..26a1796b7145 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -86,12 +86,19 @@ Required properties:
   * "qcom,dsi-phy-28nm-lp"
   * "qcom,dsi-phy-20nm"
   * "qcom,dsi-phy-28nm-8960"
-- reg: Physical base address and length of the registers of PLL, PHY and PHY
-  regulator
+  * "qcom,dsi-phy-14nm"
+- reg: Physical base address and length of the registers of PLL, PHY. Some
+  revisions require the PHY regulator base address, whereas others require the
+  PHY lane base address. See below for each PHY revision.
 - reg-names: The names of register regions. The following regions are required:
+  For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
   * "dsi_pll"
   * "dsi_phy"
   * "dsi_phy_regulator"
+  For DSI 14nm PHY:
+  * "dsi_pll"
+  * "dsi_phy"
+  * "dsi_phy_lane"
 - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
   2 clocks: A byte clock (index 0), and a pixel clock (index 1).
 - power-domains: Should be <&mmcc MDSS_GDSC>.
@@ -102,6 +109,8 @@ Required properties:
 - vddio-supply: phandle to vdd-io regulator device node
   For 20nm PHY:
 - vddio-supply: phandle to vdd-io regulator device node
+- vcca-supply: phandle to vcca regulator device node
+  For 14nm PHY:
 - vcca-supply: phandle to vcca regulator device node
 
 Optional properties:
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

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  parent reply	other threads:[~2018-01-17  9:34 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-17  9:34 [PATCH 0/7] drm/msm/dsi: SDM845 DSI host controller and DT updates Archit Taneja
2018-01-17  9:34 ` [PATCH 1/7] drm/msm/dsi: Use msm_clk_get in dsi_get_config Archit Taneja
2018-01-17  9:34 ` [PATCH 2/7] drm/msm/dsi: Add SDM845 in dsi_cfg Archit Taneja
2018-01-17  9:34 ` [PATCH 3/7] drm/msm/dsi: Add byte_intf_clk Archit Taneja
2018-01-17  9:34 ` [PATCH 4/7] dt-bindings: display: msm/dsi: Remove unused properties Archit Taneja
2018-01-29 17:11   ` Rob Herring
2018-01-17  9:34 ` [PATCH 5/7] dt-bindings: display: msm/dsi: Fix the PHY regulator supply props Archit Taneja
     [not found]   ` <20180117093448.4102-6-architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-01-29 17:13     ` Rob Herring
2018-01-17  9:34 ` Archit Taneja [this message]
2018-01-29 17:15   ` [PATCH 6/7] dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHY Rob Herring
2018-01-31  6:40     ` Archit Taneja
2018-01-31 16:20       ` Rob Clark
     [not found]         ` <CAF6AEGsLrXBUub9Y5r-bTY2OPDksRSDjYpJXYoKxYp3MvHCP2w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-02-01  5:29           ` Archit Taneja
2018-02-01 14:41             ` Rob Herring
2018-01-17  9:34 ` [PATCH 7/7] dt-bindings: display: msm/dsi: Add updates for SDM845 Archit Taneja
2018-01-29 17:16   ` Rob Herring

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