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From: Lina Iyer <ilina@codeaurora.org>
To: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com
Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	sboyd@codeaurora.org, rnayak@codeaurora.org,
	asathyak@codeaurora.org, Lina Iyer <ilina@codeaurora.org>
Subject: [PATCH RFC 4/4] drivers: irqchip: qcom: add pin information for SDM845
Date: Tue, 23 Jan 2018 10:56:56 -0700	[thread overview]
Message-ID: <20180123175656.11942-5-ilina@codeaurora.org> (raw)
In-Reply-To: <20180123175656.11942-1-ilina@codeaurora.org>

From: Archana Sathyakumar <asathyak@codeaurora.org>

Add PDC pin information for SDM845. Interrupts listed are wake up
sources for the processor, when the processor and GIC are powered down.

Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
---
 drivers/irqchip/Makefile          |   2 +-
 drivers/irqchip/qcom-pdc-sdm845.c | 130 ++++++++++++++++++++++++++++++++++++++
 drivers/irqchip/qcom-pdc.c        |   3 +
 drivers/irqchip/qcom-pdc.h        |   1 +
 4 files changed, 135 insertions(+), 1 deletion(-)
 create mode 100644 drivers/irqchip/qcom-pdc-sdm845.c

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 280723d83916..0cf8f3feb47f 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -84,4 +84,4 @@ obj-$(CONFIG_QCOM_IRQ_COMBINER)		+= qcom-irq-combiner.o
 obj-$(CONFIG_IRQ_UNIPHIER_AIDET)	+= irq-uniphier-aidet.o
 obj-$(CONFIG_ARCH_SYNQUACER)		+= irq-sni-exiu.o
 obj-$(CONFIG_MESON_IRQ_GPIO)		+= irq-meson-gpio.o
-obj-$(CONFIG_QCOM_PDC)			+= qcom-pdc.o
+obj-$(CONFIG_QCOM_PDC)			+= qcom-pdc.o qcom-pdc-sdm845.o
diff --git a/drivers/irqchip/qcom-pdc-sdm845.c b/drivers/irqchip/qcom-pdc-sdm845.c
new file mode 100644
index 000000000000..57d0fb51d5ac
--- /dev/null
+++ b/drivers/irqchip/qcom-pdc-sdm845.c
@@ -0,0 +1,130 @@
+/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include "qcom-pdc.h"
+
+const struct pdc_pin sdm845_data[] = {
+	{0, 512}, /* rpmh_wake */
+	{1, 513}, /* ee0_apps_hlos_spmi_periph_irq */
+	{2, 514}, /* ee1_apps_trustzone_spmi_periph_irq */
+	{3, 515}, /* secure_wdog_expired */
+	{4, 516}, /* secure_wdog_bark_irq */
+	{5, 517}, /* aop_wdog_expired_irq */
+	{6, 518}, /* qmp_usb3_lfps_rxterm_irq */
+	{7, 519}, /* qmp_usb3_lfps_rxterm_irq */
+	{8, 520}, /* eud_p0_dmse_int_mx */
+	{9, 521}, /* eud_p0_dpse_int_mx */
+	{10, 522}, /* eud_p1_dmse_int_mx */
+	{11, 523}, /* eud_p1_dpse_int_mx */
+	{12, 524}, /* eud_int_mx[1] */
+	{13, 525}, /* ssc_xpu_irq_summary */
+	{14, 526}, /* wd_bite_apps */
+	{15, 527}, /* ssc_vmidmt_irq_summary */
+	{16, 528}, /* q6ss_irq_out_apps_ipc[4] */
+	{17, 529}, /* not-connected */
+	{18, 530}, /* aoss_pmic_arb_mpu_xpu_summary_irq */
+	{19, 531}, /* apps_pdc_irq_in_19 */
+	{20, 532}, /* apps_pdc_irq_in_20 */
+	{21, 533}, /* apps_pdc_irq_in_21 */
+	{22, 534}, /* pdc_apps_epcb_timeout_summary_irq */
+	{23, 535}, /* spmi_protocol_irq */
+	{24, 536}, /* tsense0_tsense_max_min_int */
+	{25, 537}, /* tsense1_tsense_max_min_int */
+	{26, 538}, /* tsense0_upper_lower_intr */
+	{27, 539}, /* tsense1_upper_lower_intr */
+	{28, 540}, /* tsense0_critical_intr */
+	{29, 541}, /* tsense1_critical_intr */
+	{30, 542}, /* core_bi_px_gpio_1 */
+	{31, 543}, /* core_bi_px_gpio_3 */
+	{32, 544}, /* core_bi_px_gpio_5 */
+	{33, 545}, /* core_bi_px_gpio_10 */
+	{34, 546}, /* core_bi_px_gpio_11 */
+	{35, 547}, /* core_bi_px_gpio_20 */
+	{36, 548}, /* core_bi_px_gpio_22 */
+	{37, 549}, /* core_bi_px_gpio_24 */
+	{38, 550}, /* core_bi_px_gpio_26 */
+	{39, 551}, /* core_bi_px_gpio_30 */
+	{41, 553}, /* core_bi_px_gpio_32 */
+	{42, 554}, /* core_bi_px_gpio_34 */
+	{43, 555}, /* core_bi_px_gpio_36 */
+	{44, 556}, /* core_bi_px_gpio_37 */
+	{45, 557}, /* core_bi_px_gpio_38 */
+	{46, 558}, /* core_bi_px_gpio_39 */
+	{47, 559}, /* core_bi_px_gpio_40 */
+	{49, 561}, /* core_bi_px_gpio_43 */
+	{50, 562}, /* core_bi_px_gpio_44 */
+	{51, 563}, /* core_bi_px_gpio_46 */
+	{52, 564}, /* core_bi_px_gpio_48 */
+	{54, 566}, /* core_bi_px_gpio_52 */
+	{55, 567}, /* core_bi_px_gpio_53 */
+	{56, 568}, /* core_bi_px_gpio_54 */
+	{57, 569}, /* core_bi_px_gpio_56 */
+	{58, 570}, /* core_bi_px_gpio_57 */
+	{59, 571}, /* core_bi_px_gpio_58 */
+	{60, 572}, /* core_bi_px_gpio_59 */
+	{61, 573}, /* core_bi_px_gpio_60 */
+	{62, 574}, /* core_bi_px_gpio_61 */
+	{63, 575}, /* core_bi_px_gpio_62 */
+	{64, 576}, /* core_bi_px_gpio_63 */
+	{65, 577}, /* core_bi_px_gpio_64 */
+	{66, 578}, /* core_bi_px_gpio_66 */
+	{67, 579}, /* core_bi_px_gpio_68 */
+	{68, 580}, /* core_bi_px_gpio_71 */
+	{69, 581}, /* core_bi_px_gpio_73 */
+	{70, 582}, /* core_bi_px_gpio_77 */
+	{71, 583}, /* core_bi_px_gpio_78 */
+	{72, 584}, /* core_bi_px_gpio_79 */
+	{73, 585}, /* core_bi_px_gpio_80 */
+	{74, 586}, /* core_bi_px_gpio_84 */
+	{75, 587}, /* core_bi_px_gpio_85 */
+	{76, 588}, /* core_bi_px_gpio_86 */
+	{77, 589}, /* core_bi_px_gpio_88 */
+	{79, 591}, /* core_bi_px_gpio_91 */
+	{80, 592}, /* core_bi_px_gpio_92 */
+	{81, 593}, /* core_bi_px_gpio_95 */
+	{82, 594}, /* core_bi_px_gpio_96 */
+	{83, 595}, /* core_bi_px_gpio_97 */
+	{84, 596}, /* core_bi_px_gpio_101 */
+	{85, 597}, /* core_bi_px_gpio_103 */
+	{86, 598}, /* core_bi_px_gpio_104 */
+	{87, 599}, /* core_bi_px_to_mpm[6] */
+	{88, 600}, /* core_bi_px_to_mpm[0] */
+	{89, 601}, /* core_bi_px_to_mpm[1] */
+	{90, 602}, /* core_bi_px_gpio_115 */
+	{91, 603}, /* core_bi_px_gpio_116 */
+	{92, 604}, /* core_bi_px_gpio_117 */
+	{93, 605}, /* core_bi_px_gpio_118 */
+	{94, 641}, /* core_bi_px_gpio_119 */
+	{95, 642}, /* core_bi_px_gpio_120 */
+	{96, 643}, /* core_bi_px_gpio_121 */
+	{97, 644}, /* core_bi_px_gpio_122 */
+	{98, 645}, /* core_bi_px_gpio_123 */
+	{99, 646}, /* core_bi_px_gpio_124 */
+	{100, 647}, /* core_bi_px_gpio_125 */
+	{101, 648}, /* core_bi_px_to_mpm[5] */
+	{102, 649}, /* core_bi_px_gpio_127 */
+	{103, 650}, /* core_bi_px_gpio_128 */
+	{104, 651}, /* core_bi_px_gpio_129 */
+	{105, 652}, /* core_bi_px_gpio_130 */
+	{106, 653}, /* core_bi_px_gpio_132 */
+	{107, 654}, /* core_bi_px_gpio_133 */
+	{108, 655}, /* core_bi_px_gpio_145 */
+	{119, 666}, /* core_bi_px_to_mpm[2] */
+	{120, 667}, /* core_bi_px_to_mpm[3] */
+	{121, 668}, /* core_bi_px_to_mpm[4] */
+	{115, 662}, /* core_bi_px_gpio_41 */
+	{116, 663}, /* core_bi_px_gpio_89 */
+	{117, 664}, /* core_bi_px_gpio_31 */
+	{118, 665}, /* core_bi_px_gpio_49 */
+	{-1}
+};
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index 9b626e9f3a29..0d54db4e915b 100644
--- a/drivers/irqchip/qcom-pdc.c
+++ b/drivers/irqchip/qcom-pdc.c
@@ -241,6 +241,7 @@ static const struct irq_domain_ops qcom_pdc_ops = {
 };
 
 static const struct of_device_id pdc_table[] = {
+	{ .compatible = "qcom,pdc-sdm845", .data = sdm845_data, },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, pdc_table);
@@ -286,3 +287,5 @@ int qcom_pdc_init(struct device_node *node, struct device_node *parent)
 	iounmap(pdc_base);
 	return ret;
 }
+
+IRQCHIP_DECLARE(pdc_sdm845, "qcom,pdc-sdm845", qcom_pdc_init);
diff --git a/drivers/irqchip/qcom-pdc.h b/drivers/irqchip/qcom-pdc.h
index b5b64390175e..6a9d9f9eb4f1 100644
--- a/drivers/irqchip/qcom-pdc.h
+++ b/drivers/irqchip/qcom-pdc.h
@@ -27,4 +27,5 @@ struct pdc_pin {
 	irq_hw_number_t hwirq;
 };
 
+extern const struct pdc_pin sdm845_data[];
 #endif /* __QCOM_PDC_H__ */
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

  parent reply	other threads:[~2018-01-23 17:56 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-23 17:56 [PATCH RFC 0/4] irqchip: qcom: add support for PDC interrupt controller Lina Iyer
2018-01-23 17:56 ` [PATCH RFC 1/4] drivers: irqchip: pdc: " Lina Iyer
2018-01-24 14:20   ` Marc Zyngier
2018-01-25 18:52     ` Lina Iyer
2018-01-30 17:56     ` Lina Iyer
2018-01-30 18:11       ` Marc Zyngier
2018-01-31 16:24         ` Lina Iyer
2018-01-31 16:46           ` Marc Zyngier
2018-02-01 16:49             ` Lina Iyer
2018-01-23 17:56 ` [PATCH RFC 2/4] dt-bindings/interrupt-controller: pdc: descibe PDC device binding Lina Iyer
2018-01-23 18:09   ` Sudeep Holla
2018-01-23 18:46     ` Lina Iyer
2018-01-24 14:24   ` Marc Zyngier
2018-01-30 15:20   ` Rob Herring
2018-01-23 17:56 ` [PATCH RFC 3/4] drivers: irqchip: pdc: log PDC info in FTRACE Lina Iyer
2018-01-23 18:13   ` Steven Rostedt
2018-01-25 15:45     ` Lina Iyer
2018-01-23 17:56 ` Lina Iyer [this message]
2018-01-24 14:20   ` [PATCH RFC 4/4] drivers: irqchip: qcom: add pin information for SDM845 Marc Zyngier
2018-01-25 18:14     ` Lina Iyer
2018-01-23 18:15 ` [PATCH RFC 0/4] irqchip: qcom: add support for PDC interrupt controller Sudeep Holla
2018-01-23 18:44   ` Lina Iyer
2018-01-24 10:10     ` Sudeep Holla
2018-01-24 17:43       ` Lina Iyer
2018-01-24 17:54         ` Sudeep Holla
2018-01-25 15:54           ` Lina Iyer
2018-01-25 16:39             ` Sudeep Holla
2018-01-25 18:13               ` Lina Iyer
2018-01-25 18:43                 ` Sudeep Holla
2018-01-25 20:05                   ` Lina Iyer
2018-01-26 11:39                     ` Sudeep Holla

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