[PATCH] drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence

[PATCH] drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence

[Hans de Goede]

So far models of the Dell Venue 8 Pro, with a panel with MIPI panel
index = 3, one of which has been kindly provided to me by Jan Brummer,
where not working with the i915 driver, giving a black screen on the
first modeset.

The problem with at least these Dells is that their VBT defines a MIPI
ASSERT sequence, but not a DEASSERT sequence. Instead they DEASSERT the
reset in their INIT_OTP sequence, but the deassert must be done before
calling intel_dsi_device_ready(), so that is too late.

Simply doing the INIT_OTP sequence earlier is not enough to fix this,
because the INIT_OTP sequence also sends various MIPI packets to the
panel, which can only happen after calling intel_dsi_device_ready().

This commit fixes this by making mipi_exec_send_packet() call
intel_dsi_device_ready() if not done already, so that we can call the
INIT_OTP sequence earlier on affected devices.

Note that this only changes the init-sequence on devices for which
intel_dsi_use_init_otp_as_deassert() returns true, on other devices
intel_dsi->device_ready will be set to true before calling any
MIPI sequences which may send packets, so the check added to
mipi_exec_send_packet() is a nop there.

BugLink: https://bugs.freedesktop.org/show_bug.cgi?id=82880
Related: https://bugs.freedesktop.org/show_bug.cgi?id=101205
Reported-by: Jan-Michael Brummer <jan.brummer@tabos.org>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/gpu/drm/i915/intel_dsi.c     | 53 ++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_dsi.h     |  4 +++
 drivers/gpu/drm/i915/intel_dsi_vbt.c |  6 ++++
 3 files changed, 60 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index f67d321376e4..3d82811a38f3 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -539,9 +539,14 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 	}
 }
 
-static void intel_dsi_device_ready(struct intel_encoder *encoder)
+void intel_dsi_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+
+	/* Already done? */
+	if (intel_dsi->device_ready)
+		return;
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		vlv_dsi_device_ready(encoder);
@@ -549,6 +554,8 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 		bxt_dsi_device_ready(encoder);
 	else if (IS_GEMINILAKE(dev_priv))
 		glk_dsi_device_ready(encoder);
+
+	intel_dsi->device_ready = true;
 }
 
 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
@@ -786,6 +793,36 @@ static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
  * - wait t4                                           - wait t4
  */
 
+/*
+ * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence.
+ * The deassert must be done before calling intel_dsi_device_ready, while
+ * intel_dsi_device_ready() must be called before any send packet ops inside
+ * the init OTP sequence. mipi_exec_send_packet() deals with calling
+ * intel_dsi_device_ready() if necessary. This function checks if we need
+ * to call init OTP at deassert time.
+ */
+static bool intel_dsi_use_init_otp_as_deassert(struct intel_dsi *intel_dsi)
+{
+	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+
+	/* Limit this to VLV for now. */
+	if (!IS_VALLEYVIEW(dev_priv))
+		return false;
+
+	/* Limit this to v1 vid-mode sequences */
+	if (!is_vid_mode(intel_dsi) || dev_priv->vbt.dsi.seq_version != 1)
+		return false;
+
+	/* If there is an assert-reset seq and no deassert one, use init OTP */
+	if (dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] != 0 &&
+	    dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] == 0) {
+		DRM_DEBUG_KMS("Using init OTP to deassert reset\n");
+		return true;
+	}
+
+	return false;
+}
+
 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *pipe_config,
 				 const struct drm_connector_state *conn_state)
@@ -840,7 +877,10 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 	intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 
 	/* Deassert reset */
-	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
+	if (intel_dsi_use_init_otp_as_deassert(intel_dsi))
+		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
+	else
+		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 
 	if (IS_GEMINILAKE(dev_priv)) {
 		glk_cold_boot = glk_dsi_enable_io(encoder);
@@ -858,7 +898,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 		intel_dsi_prepare(encoder, pipe_config);
 
 	/* Send initialization commands in LP mode */
-	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
+	if (!intel_dsi_use_init_otp_as_deassert(intel_dsi))
+		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 
 	/* Enable port in pre-enable phase itself because as per hw team
 	 * recommendation, port should be enabled befor plane & pipe */
@@ -925,12 +966,15 @@ static void intel_dsi_disable(struct intel_encoder *encoder,
 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
 	    IS_BROXTON(dev_priv))
 		vlv_dsi_clear_device_ready(encoder);
 	else if (IS_GEMINILAKE(dev_priv))
 		glk_dsi_clear_device_ready(encoder);
+
+	intel_dsi->device_ready = false;
 }
 
 static void intel_dsi_post_disable(struct intel_encoder *encoder,
@@ -944,6 +988,9 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
 
 	DRM_DEBUG_KMS("\n");
 
+	/* in case the dsi panel is on when the i915 driver gets loaded */
+	intel_dsi->device_ready = true;
+
 	if (is_vid_mode(intel_dsi)) {
 		for_each_dsi_port(port, intel_dsi->ports)
 			wait_for_dsi_fifo_empty(intel_dsi, port);
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 7afeb9580f41..d501cbcc97d0 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -46,6 +46,9 @@ struct intel_dsi {
 
 	struct intel_connector *attached_connector;
 
+	/* Have we put the device in ready state (LP-11) ? */
+	bool device_ready;
+
 	/* bit mask of ports being driven */
 	u16 ports;
 
@@ -132,6 +135,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
 /* intel_dsi.c */
 void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
+void intel_dsi_device_ready(struct intel_encoder *encoder);
 
 /* intel_dsi_pll.c */
 bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 91c07b0c8db9..cf4e9e2a8df1 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -118,6 +118,12 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
 
 	DRM_DEBUG_KMS("\n");
 
+	/* Make sure the device is in ready state (LP-11) */
+	if (!intel_dsi->device_ready) {
+		intel_dsi_device_ready(&intel_dsi->base);
+		usleep_range(10000, 20000);
+	}
+
 	flags = *data++;
 	type = *data++;
 
-- 
2.14.3

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence

[Ville Syrjälä]

On Thu, Jan 25, 2018 at 02:37:26PM +0100, Hans de Goede wrote:
> So far models of the Dell Venue 8 Pro, with a panel with MIPI panel
> index = 3, one of which has been kindly provided to me by Jan Brummer,
> where not working with the i915 driver, giving a black screen on the
> first modeset.
> 
> The problem with at least these Dells is that their VBT defines a MIPI
> ASSERT sequence, but not a DEASSERT sequence. Instead they DEASSERT the
> reset in their INIT_OTP sequence, but the deassert must be done before
> calling intel_dsi_device_ready(), so that is too late.
> 
> Simply doing the INIT_OTP sequence earlier is not enough to fix this,
> because the INIT_OTP sequence also sends various MIPI packets to the
> panel, which can only happen after calling intel_dsi_device_ready().
> 
> This commit fixes this by making mipi_exec_send_packet() call
> intel_dsi_device_ready() if not done already, so that we can call the
> INIT_OTP sequence earlier on affected devices.
> 
> Note that this only changes the init-sequence on devices for which
> intel_dsi_use_init_otp_as_deassert() returns true, on other devices
> intel_dsi->device_ready will be set to true before calling any
> MIPI sequences which may send packets, so the check added to
> mipi_exec_send_packet() is a nop there.

I don't like how wide this kludge spreads in the code.

Could we instead just extract the deassert sequence from the
OTP sequence? Looks like your code already assumes that everything
up to the first DSI packet is part of the deassert sequence. So
I imagine it should be pretty easy to split the sequence up at
that same point?

> 
> BugLink: https://bugs.freedesktop.org/show_bug.cgi?id=82880
> Related: https://bugs.freedesktop.org/show_bug.cgi?id=101205
> Reported-by: Jan-Michael Brummer <jan.brummer@tabos.org>
> Tested-by: Hans de Goede <hdegoede@redhat.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c     | 53 ++++++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_dsi.h     |  4 +++
>  drivers/gpu/drm/i915/intel_dsi_vbt.c |  6 ++++
>  3 files changed, 60 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index f67d321376e4..3d82811a38f3 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -539,9 +539,14 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
>  	}
>  }
>  
> -static void intel_dsi_device_ready(struct intel_encoder *encoder)
> +void intel_dsi_device_ready(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +
> +	/* Already done? */
> +	if (intel_dsi->device_ready)
> +		return;
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		vlv_dsi_device_ready(encoder);
> @@ -549,6 +554,8 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>  		bxt_dsi_device_ready(encoder);
>  	else if (IS_GEMINILAKE(dev_priv))
>  		glk_dsi_device_ready(encoder);
> +
> +	intel_dsi->device_ready = true;
>  }
>  
>  static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
> @@ -786,6 +793,36 @@ static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
>   * - wait t4                                           - wait t4
>   */
>  
> +/*
> + * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence.
> + * The deassert must be done before calling intel_dsi_device_ready, while
> + * intel_dsi_device_ready() must be called before any send packet ops inside
> + * the init OTP sequence. mipi_exec_send_packet() deals with calling
> + * intel_dsi_device_ready() if necessary. This function checks if we need
> + * to call init OTP at deassert time.
> + */
> +static bool intel_dsi_use_init_otp_as_deassert(struct intel_dsi *intel_dsi)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
> +
> +	/* Limit this to VLV for now. */
> +	if (!IS_VALLEYVIEW(dev_priv))
> +		return false;
> +
> +	/* Limit this to v1 vid-mode sequences */
> +	if (!is_vid_mode(intel_dsi) || dev_priv->vbt.dsi.seq_version != 1)
> +		return false;
> +
> +	/* If there is an assert-reset seq and no deassert one, use init OTP */
> +	if (dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] != 0 &&
> +	    dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] == 0) {
> +		DRM_DEBUG_KMS("Using init OTP to deassert reset\n");
> +		return true;
> +	}
> +
> +	return false;
> +}
> +
>  static void intel_dsi_pre_enable(struct intel_encoder *encoder,
>  				 const struct intel_crtc_state *pipe_config,
>  				 const struct drm_connector_state *conn_state)
> @@ -840,7 +877,10 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
>  	intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
>  
>  	/* Deassert reset */
> -	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
> +	if (intel_dsi_use_init_otp_as_deassert(intel_dsi))
> +		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
> +	else
> +		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
>  
>  	if (IS_GEMINILAKE(dev_priv)) {
>  		glk_cold_boot = glk_dsi_enable_io(encoder);
> @@ -858,7 +898,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
>  		intel_dsi_prepare(encoder, pipe_config);
>  
>  	/* Send initialization commands in LP mode */
> -	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
> +	if (!intel_dsi_use_init_otp_as_deassert(intel_dsi))
> +		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
>  
>  	/* Enable port in pre-enable phase itself because as per hw team
>  	 * recommendation, port should be enabled befor plane & pipe */
> @@ -925,12 +966,15 @@ static void intel_dsi_disable(struct intel_encoder *encoder,
>  static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
>  	    IS_BROXTON(dev_priv))
>  		vlv_dsi_clear_device_ready(encoder);
>  	else if (IS_GEMINILAKE(dev_priv))
>  		glk_dsi_clear_device_ready(encoder);
> +
> +	intel_dsi->device_ready = false;
>  }
>  
>  static void intel_dsi_post_disable(struct intel_encoder *encoder,
> @@ -944,6 +988,9 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
>  
>  	DRM_DEBUG_KMS("\n");
>  
> +	/* in case the dsi panel is on when the i915 driver gets loaded */
> +	intel_dsi->device_ready = true;
> +
>  	if (is_vid_mode(intel_dsi)) {
>  		for_each_dsi_port(port, intel_dsi->ports)
>  			wait_for_dsi_fifo_empty(intel_dsi, port);
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 7afeb9580f41..d501cbcc97d0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -46,6 +46,9 @@ struct intel_dsi {
>  
>  	struct intel_connector *attached_connector;
>  
> +	/* Have we put the device in ready state (LP-11) ? */
> +	bool device_ready;
> +
>  	/* bit mask of ports being driven */
>  	u16 ports;
>  
> @@ -132,6 +135,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
>  /* intel_dsi.c */
>  void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
>  enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
> +void intel_dsi_device_ready(struct intel_encoder *encoder);
>  
>  /* intel_dsi_pll.c */
>  bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index 91c07b0c8db9..cf4e9e2a8df1 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -118,6 +118,12 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
>  
>  	DRM_DEBUG_KMS("\n");
>  
> +	/* Make sure the device is in ready state (LP-11) */
> +	if (!intel_dsi->device_ready) {
> +		intel_dsi_device_ready(&intel_dsi->base);
> +		usleep_range(10000, 20000);
> +	}
> +
>  	flags = *data++;
>  	type = *data++;
>  
> -- 
> 2.14.3

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence

[Patchwork]

== Series Details ==

Series: drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence
URL   : https://patchwork.freedesktop.org/series/37105/
State : success

== Summary ==

Series 37105v1 drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence
https://patchwork.freedesktop.org/api/1.0/series/37105/revisions/1/mbox/

Test debugfs_test:
        Subgroup read_all_entries:
                pass       -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:428s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:428s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:374s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:483s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:281s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:479s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:483s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:467s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:455s
fi-elk-e7500     total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:278s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:513s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:390s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:399s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:412s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:454s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:420s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:457s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:499s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:452s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:504s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:578s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:430s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:510s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:531s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:484s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:480s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:419s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:429s
fi-snb-2520m     total:3    pass:2    dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:400s
Blacklisted hosts:
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:558s
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:472s

9d8467fe5626095314bc34449457798dae066fbb drm-tip: 2018y-01m-24d-19h-59m-41s UTC integration manifest
5178f7cd2768 drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7778/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence

[Patchwork]

== Series Details ==

Series: drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence
URL   : https://patchwork.freedesktop.org/series/37105/
State : failure

== Summary ==

Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
                pass       -> FAIL       (shard-apl) fdo#101623 +1
Test kms_sysfs_edid_timing:
                pass       -> WARN       (shard-apl) fdo#100047
Test kms_flip:
        Subgroup plain-flip-fb-recreate-interruptible:
                fail       -> PASS       (shard-hsw) fdo#100368 +1
        Subgroup 2x-flip-vs-modeset-interruptible:
                dmesg-warn -> PASS       (shard-hsw) fdo#102614
Test kms_universal_plane:
        Subgroup universal-plane-pipe-b-functional:
                pass       -> FAIL       (shard-apl)
Test perf:
        Subgroup buffer-fill:
                pass       -> FAIL       (shard-apl) fdo#103755

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755

shard-apl        total:2838 pass:1747 dwarn:1   dfail:0   fail:27  skip:1062 time:12614s
shard-hsw        total:2838 pass:1734 dwarn:1   dfail:0   fail:12  skip:1090 time:11904s
shard-snb        total:2838 pass:1330 dwarn:1   dfail:0   fail:10  skip:1497 time:6614s
Blacklisted hosts:
shard-kbl        total:2820 pass:1856 dwarn:1   dfail:0   fail:23  skip:939 time:9417s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7778/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence

[Hans de Goede]

Hi,

On 25-01-18 15:10, Ville Syrjälä wrote:
> On Thu, Jan 25, 2018 at 02:37:26PM +0100, Hans de Goede wrote:
>> So far models of the Dell Venue 8 Pro, with a panel with MIPI panel
>> index = 3, one of which has been kindly provided to me by Jan Brummer,
>> where not working with the i915 driver, giving a black screen on the
>> first modeset.
>>
>> The problem with at least these Dells is that their VBT defines a MIPI
>> ASSERT sequence, but not a DEASSERT sequence. Instead they DEASSERT the
>> reset in their INIT_OTP sequence, but the deassert must be done before
>> calling intel_dsi_device_ready(), so that is too late.
>>
>> Simply doing the INIT_OTP sequence earlier is not enough to fix this,
>> because the INIT_OTP sequence also sends various MIPI packets to the
>> panel, which can only happen after calling intel_dsi_device_ready().
>>
>> This commit fixes this by making mipi_exec_send_packet() call
>> intel_dsi_device_ready() if not done already, so that we can call the
>> INIT_OTP sequence earlier on affected devices.
>>
>> Note that this only changes the init-sequence on devices for which
>> intel_dsi_use_init_otp_as_deassert() returns true, on other devices
>> intel_dsi->device_ready will be set to true before calling any
>> MIPI sequences which may send packets, so the check added to
>> mipi_exec_send_packet() is a nop there.
> 
> I don't like how wide this kludge spreads in the code.
> 
> Could we instead just extract the deassert sequence from the
> OTP sequence? Looks like your code already assumes that everything
> up to the first DSI packet is part of the deassert sequence. So
> I imagine it should be pretty easy to split the sequence up at
> that same point?

Good idea, I've implemented this it results in slightly more code,
but is a lot cleaner indeed.

v2 with this new approach is coming up...

Regards,

Hans
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel