[PATCH 0/6] ICL display initialization, selected patches

[PATCH 0/6] ICL display initialization, selected patches

[Paulo Zanoni]

Hi

These are 6 selected patches form the series "ICL display
initialization and some plane bits". Only patch 2 still needs review,
the others are already reviewed.

The original series of 17 patches triggered some CI errors that
definitely seem to be the fault of the series. Some of the patches
were reviewed and then sent as part of a new series and were merged
because they didn't trigger the CI failures. Now I'm sending another
subset of the patches in the hope that the CI failures won't be
triggered again. Then we'll only have a few remaining patches to
investigate the problem later.

Thanks,
Paulo

Mahesh Kumar (3):
  drm/i915/icl: Enable both DBuf slices during init
  drm/i915/icl: initialize MBus during display init
  drm/i915/icl: program mbus during pipe enable

Paulo Zanoni (3):
  drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
  drm/i915/icl: add the main CDCLK functions
  drm/i915/icl: implement the display init/uninit sequences

 drivers/gpu/drm/i915/i915_reg.h         |  75 +++++++---
 drivers/gpu/drm/i915/intel_cdclk.c      | 235 +++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_display.c    |  20 +++
 drivers/gpu/drm/i915/intel_drv.h        |   2 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 146 ++++++++++++++++++--
 5 files changed, 450 insertions(+), 28 deletions(-)

-- 
2.14.3

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[PATCH 1/6] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

[Paulo Zanoni]

On ICL we have two sets of registers: one for port A and another for
port B. The set of port A registers is the same as the CNL registers.

Since the procmon table on ICL is the same we want to reuse the CNL
function. To do that we add a port argument and make CNL always call
the function passing port A. This way, we'll be able to easily reuse
the function on ICL when we add icl_display_core_init().

v2: Don't use _PICK() when you can use a ternary operator.
v3: Don't use a ternary operation when you can use _MMIO_PORT (Ville).
    Add an extra comment about why we're passing PORT_A (James).

Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 22 ++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++++++++++++++-------
 2 files changed, 37 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 65ba10ad1fe5..f6e1677e8211 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2104,6 +2104,28 @@ enum i915_power_well_id {
 #define CNL_PORT_COMP_DW9		_MMIO(0x162124)
 #define CNL_PORT_COMP_DW10		_MMIO(0x162128)
 
+#define _ICL_PORT_COMP_DW0_A		0x162100
+#define _ICL_PORT_COMP_DW0_B		0x6C100
+#define ICL_PORT_COMP_DW0(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
+							 _ICL_PORT_COMP_DW0_B)
+#define _ICL_PORT_COMP_DW1_A		0x162104
+#define _ICL_PORT_COMP_DW1_B		0x6C104
+#define ICL_PORT_COMP_DW1(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
+							 _ICL_PORT_COMP_DW1_B)
+#define _ICL_PORT_COMP_DW3_A		0x16210C
+#define _ICL_PORT_COMP_DW3_B		0x6C10C
+#define ICL_PORT_COMP_DW3(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
+							 _ICL_PORT_COMP_DW3_B)
+#define _ICL_PORT_COMP_DW9_A		0x162124
+#define _ICL_PORT_COMP_DW9_B		0x6C124
+#define ICL_PORT_COMP_DW9(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
+							 _ICL_PORT_COMP_DW9_B)
+#define _ICL_PORT_COMP_DW10_A		0x162128
+#define _ICL_PORT_COMP_DW10_B		0x6C128
+#define ICL_PORT_COMP_DW10(port)	_MMIO_PORT(port, \
+						   _ICL_PORT_COMP_DW10_A, \
+						   _ICL_PORT_COMP_DW10_B)
+
 /* BXT PHY Ref registers */
 #define _PORT_REF_DW3_A			0x16218C
 #define _PORT_REF_DW3_BC		0x6C18C
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 70e659772a7a..b4ef7875f055 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2794,12 +2794,19 @@ static const struct cnl_procmon {
 		{ .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
 };
 
-static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
+/*
+ * CNL has just one set of registers, while ICL has two sets: one for port A and
+ * the other for port B. The CNL registers are equivalent to the ICL port A
+ * registers, that's why we call the ICL macros even though the function has CNL
+ * on its name.
+ */
+static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
+				       enum port port)
 {
 	const struct cnl_procmon *procmon;
 	u32 val;
 
-	val = I915_READ(CNL_PORT_COMP_DW3);
+	val = I915_READ(ICL_PORT_COMP_DW3(port));
 	switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
 	default:
 		MISSING_CASE(val);
@@ -2820,13 +2827,13 @@ static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
 		break;
 	}
 
-	val = I915_READ(CNL_PORT_COMP_DW1);
+	val = I915_READ(ICL_PORT_COMP_DW1(port));
 	val &= ~((0xff << 16) | 0xff);
 	val |= procmon->dw1;
-	I915_WRITE(CNL_PORT_COMP_DW1, val);
+	I915_WRITE(ICL_PORT_COMP_DW1(port), val);
 
-	I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
-	I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
+	I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
+	I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
 }
 
 static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
@@ -2847,7 +2854,8 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
 	val &= ~CNL_COMP_PWR_DOWN;
 	I915_WRITE(CHICKEN_MISC_2, val);
 
-	cnl_set_procmon_ref_values(dev_priv);
+	/* Dummy PORT_A to get the correct CNL register from the ICL macro */
+	cnl_set_procmon_ref_values(dev_priv, PORT_A);
 
 	val = I915_READ(CNL_PORT_COMP_DW0);
 	val |= COMP_INIT;
-- 
2.14.3

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[PATCH 2/6] drm/i915/icl: add the main CDCLK functions

[Paulo Zanoni]

This commit adds the basic CDCLK functions, but it's still missing
pieces of the display initialization sequence.

v2:
 - Implement the voltage levels.
 - Rebase.
v3:
 - Adjust to the new "bypass" clock (Imre).
 - Call intel_dump_cdclk_state() too.
 - Rename a variable to avoid confusion.
 - Simplify the DVFS part.
v4:
 - Remove wrong bit definition (James).
 - Also drive-by fix the coding style for the register definition we
   touched.

Cc: James Ausmus <james.ausmus@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    |  35 +++---
 drivers/gpu/drm/i915/intel_cdclk.c | 235 ++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h   |   2 +
 3 files changed, 255 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6e1677e8211..2b6a908056d6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7182,8 +7182,12 @@ enum {
 #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
 #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
 
-#define SKL_DSSM			_MMIO(0x51004)
-#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz	(1 << 31)
+#define SKL_DSSM				_MMIO(0x51004)
+#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK		(7 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz		(0 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz	(1 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz	(2 << 29)
 
 #define GEN7_FF_SLICE_CS_CHICKEN1	_MMIO(0x20e0)
 #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL	(1<<14)
@@ -8816,20 +8820,21 @@ enum skl_power_gate {
 
 /* CDCLK_CTL */
 #define CDCLK_CTL			_MMIO(0x46000)
-#define  CDCLK_FREQ_SEL_MASK		(3<<26)
-#define  CDCLK_FREQ_450_432		(0<<26)
-#define  CDCLK_FREQ_540			(1<<26)
-#define  CDCLK_FREQ_337_308		(2<<26)
-#define  CDCLK_FREQ_675_617		(3<<26)
-#define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_1	(0<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_2	(2<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)
-#define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe)<<20)
-#define  CDCLK_DIVMUX_CD_OVERRIDE	(1<<19)
+#define  CDCLK_FREQ_SEL_MASK		(3 << 26)
+#define  CDCLK_FREQ_450_432		(0 << 26)
+#define  CDCLK_FREQ_540			(1 << 26)
+#define  CDCLK_FREQ_337_308		(2 << 26)
+#define  CDCLK_FREQ_675_617		(3 << 26)
+#define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_1	(0 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_2	(2 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_4	(3 << 22)
+#define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
+#define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
 #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
-#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
+#define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
+#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1 << 16)
 #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
 
 /* LCPLL_CTL */
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index ee788d5be5e3..52a15d0eaae9 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1778,6 +1778,197 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	dev_priv->cdclk.hw.vco = -1;
 }
 
+static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
+{
+	int ranges_24[] = { 312000, 552000, 648000 };
+	int ranges_19_38[] = { 307200, 556800, 652800 };
+	int *ranges;
+
+	switch (ref) {
+	default:
+		MISSING_CASE(ref);
+	case 24000:
+		ranges = ranges_24;
+		break;
+	case 19200:
+	case 38400:
+		ranges = ranges_19_38;
+		break;
+	}
+
+	if (min_cdclk > ranges[1])
+		return ranges[2];
+	else if (min_cdclk > ranges[0])
+		return ranges[1];
+	else
+		return ranges[0];
+}
+
+static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
+{
+	int ratio;
+
+	if (cdclk == dev_priv->cdclk.hw.bypass)
+		return 0;
+
+	switch (cdclk) {
+	default:
+		MISSING_CASE(cdclk);
+	case 307200:
+	case 556800:
+	case 652800:
+		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
+			dev_priv->cdclk.hw.ref != 38400);
+		break;
+	case 312000:
+	case 552000:
+	case 648000:
+		WARN_ON(dev_priv->cdclk.hw.ref != 24000);
+	}
+
+	ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
+
+	return dev_priv->cdclk.hw.ref * ratio;
+}
+
+static void icl_set_cdclk(struct drm_i915_private *dev_priv,
+			  const struct intel_cdclk_state *cdclk_state)
+{
+	unsigned int cdclk = cdclk_state->cdclk;
+	unsigned int vco = cdclk_state->vco;
+	int ret;
+
+	mutex_lock(&dev_priv->pcu_lock);
+	ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+				SKL_CDCLK_PREPARE_FOR_CHANGE,
+				SKL_CDCLK_READY_FOR_CHANGE,
+				SKL_CDCLK_READY_FOR_CHANGE, 3);
+	mutex_unlock(&dev_priv->pcu_lock);
+	if (ret) {
+		DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
+			  ret);
+		return;
+	}
+
+	if (dev_priv->cdclk.hw.vco != 0 &&
+	    dev_priv->cdclk.hw.vco != vco)
+		cnl_cdclk_pll_disable(dev_priv);
+
+	if (dev_priv->cdclk.hw.vco != vco)
+		cnl_cdclk_pll_enable(dev_priv, vco);
+
+	I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
+			      skl_cdclk_decimal(cdclk));
+
+	mutex_lock(&dev_priv->pcu_lock);
+	/* TODO: add proper DVFS support. */
+	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 2);
+	mutex_unlock(&dev_priv->pcu_lock);
+
+	intel_update_cdclk(dev_priv);
+}
+
+static void icl_get_cdclk(struct drm_i915_private *dev_priv,
+			  struct intel_cdclk_state *cdclk_state)
+{
+	u32 val;
+
+	cdclk_state->bypass = 50000;
+
+	val = I915_READ(SKL_DSSM);
+	switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
+	default:
+		MISSING_CASE(val);
+	case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
+		cdclk_state->ref = 24000;
+		break;
+	case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
+		cdclk_state->ref = 19200;
+		break;
+	case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
+		cdclk_state->ref = 38400;
+		break;
+	}
+
+	val = I915_READ(BXT_DE_PLL_ENABLE);
+	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
+	    (val & BXT_DE_PLL_LOCK) == 0) {
+		/* CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
+		 * setting it to zero is a way to signal that. */
+		cdclk_state->vco = 0;
+		cdclk_state->cdclk = cdclk_state->bypass;
+		return;
+	}
+
+	cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
+
+	val = I915_READ(CDCLK_CTL);
+	WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
+
+	cdclk_state->cdclk = cdclk_state->vco / 2;
+}
+
+/**
+ * icl_init_cdclk - Initialize CDCLK on ICL
+ * @dev_priv: i915 device
+ *
+ * Initialize CDCLK for ICL. This consists mainly of initializing
+ * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This
+ * is generally done only during the display core initialization sequence, after
+ * which the DMC will take care of turning CDCLK off/on as needed.
+ */
+void icl_init_cdclk(struct drm_i915_private *dev_priv)
+{
+	struct intel_cdclk_state sanitized_state;
+	u32 val;
+
+	/* This sets dev_priv->cdclk.hw. */
+	intel_update_cdclk(dev_priv);
+	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
+
+	/* This means CDCLK disabled. */
+	if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
+		goto sanitize;
+
+	val = I915_READ(CDCLK_CTL);
+
+	if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
+		goto sanitize;
+
+	if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
+	    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
+		goto sanitize;
+
+	return;
+
+sanitize:
+	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
+
+	sanitized_state.ref = dev_priv->cdclk.hw.ref;
+	sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
+	sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
+						     sanitized_state.cdclk);
+
+	icl_set_cdclk(dev_priv, &sanitized_state);
+}
+
+/**
+ * icl_uninit_cdclk - Uninitialize CDCLK on ICL
+ * @dev_priv: i915 device
+ *
+ * Uninitialize CDCLK for ICL. This is done only during the display core
+ * uninitialization sequence.
+ */
+void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
+{
+	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
+
+	cdclk_state.cdclk = cdclk_state.bypass;
+	cdclk_state.vco = 0;
+
+	icl_set_cdclk(dev_priv, &cdclk_state);
+}
+
 /**
  * cnl_init_cdclk - Initialize CDCLK on CNL
  * @dev_priv: i915 device
@@ -2216,6 +2407,36 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
 	return 0;
 }
 
+static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->dev);
+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+	unsigned int ref = intel_state->cdclk.logical.ref;
+	int min_cdclk, cdclk, vco;
+
+	min_cdclk = intel_compute_min_cdclk(state);
+	if (min_cdclk < 0)
+		return min_cdclk;
+
+	cdclk = icl_calc_cdclk(min_cdclk, ref);
+	vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
+
+	intel_state->cdclk.logical.vco = vco;
+	intel_state->cdclk.logical.cdclk = cdclk;
+
+	if (!intel_state->active_crtcs) {
+		cdclk = icl_calc_cdclk(0, ref);
+		vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
+
+		intel_state->cdclk.actual.vco = vco;
+		intel_state->cdclk.actual.cdclk = cdclk;
+	} else {
+		intel_state->cdclk.actual = intel_state->cdclk.logical;
+	}
+
+	return 0;
+}
+
 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
 {
 	int max_cdclk_freq = dev_priv->max_cdclk_freq;
@@ -2249,7 +2470,12 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
-	if (IS_CANNONLAKE(dev_priv)) {
+	if (IS_ICELAKE(dev_priv)) {
+		if (dev_priv->cdclk.hw.ref == 24000)
+			dev_priv->max_cdclk_freq = 648000;
+		else
+			dev_priv->max_cdclk_freq = 652800;
+	} else if (IS_CANNONLAKE(dev_priv)) {
 		dev_priv->max_cdclk_freq = 528000;
 	} else if (IS_GEN9_BC(dev_priv)) {
 		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
@@ -2473,9 +2699,14 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.set_cdclk = cnl_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk =
 			cnl_modeset_calc_cdclk;
+	} else if (IS_ICELAKE(dev_priv)) {
+		dev_priv->display.set_cdclk = icl_set_cdclk;
+		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
 	}
 
-	if (IS_CANNONLAKE(dev_priv))
+	if (IS_ICELAKE(dev_priv))
+		dev_priv->display.get_cdclk = icl_get_cdclk;
+	else if (IS_CANNONLAKE(dev_priv))
 		dev_priv->display.get_cdclk = cnl_get_cdclk;
 	else if (IS_GEN9_BC(dev_priv))
 		dev_priv->display.get_cdclk = skl_get_cdclk;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d6a808374dfb..cca7ecae5cce 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1403,6 +1403,8 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv);
 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
+void icl_init_cdclk(struct drm_i915_private *dev_priv);
+void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
 void intel_update_cdclk(struct drm_i915_private *dev_priv);
-- 
2.14.3

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Re: [PATCH 2/6] drm/i915/icl: add the main CDCLK functions

[Ausmus, James]

On Mon, Feb 05, 2018 at 01:40:42PM -0200, Paulo Zanoni wrote:
> This commit adds the basic CDCLK functions, but it's still missing
> pieces of the display initialization sequence.
>
> v2:
>  - Implement the voltage levels.
>  - Rebase.
> v3:
>  - Adjust to the new "bypass" clock (Imre).
>  - Call intel_dump_cdclk_state() too.
>  - Rename a variable to avoid confusion.
>  - Simplify the DVFS part.
     ^^^^^^^
Shouldn't this be something more like

"Drop DVFS part and replace with a TODO"?

"Simplify" makes it sound like it's still there, but it's not, unless
I'm missing something?


> v4:
>  - Remove wrong bit definition (James).
>  - Also drive-by fix the coding style for the register definition we
>    touched.
>
> Cc: James Ausmus <james.ausmus@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h    |  35 +++---
>  drivers/gpu/drm/i915/intel_cdclk.c | 235 ++++++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_drv.h   |   2 +
>  3 files changed, 255 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f6e1677e8211..2b6a908056d6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7182,8 +7182,12 @@ enum {
>  #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
>  #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
>  
> -#define SKL_DSSM _MMIO(0x51004)
> -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> +#define SKL_DSSM _MMIO(0x51004)
> +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
>  
>  #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
>  #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
> @@ -8816,20 +8820,21 @@ enum skl_power_gate {
>  
>  /* CDCLK_CTL */
>  #define CDCLK_CTL _MMIO(0x46000)
> -#define  CDCLK_FREQ_SEL_MASK (3<<26)
> -#define  CDCLK_FREQ_450_432 (0<<26)
> -#define  CDCLK_FREQ_540 (1<<26)
> -#define  CDCLK_FREQ_337_308 (2<<26)
> -#define  CDCLK_FREQ_675_617 (3<<26)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
> -#define  BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20)
> -#define  CDCLK_DIVMUX_CD_OVERRIDE (1<<19)
> +#define  CDCLK_FREQ_SEL_MASK (3 << 26)
> +#define  CDCLK_FREQ_450_432 (0 << 26)
> +#define  CDCLK_FREQ_540 (1 << 26)
> +#define  CDCLK_FREQ_337_308 (2 << 26)
> +#define  CDCLK_FREQ_675_617 (3 << 26)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22)
> +#define  BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
> +#define  CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
>  #define  BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
> -#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
> +#define  ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
> +#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
>  #define  CDCLK_FREQ_DECIMAL_MASK (0x7ff)
>  
>  /* LCPLL_CTL */
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index ee788d5be5e3..52a15d0eaae9 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1778,6 +1778,197 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>   dev_priv->cdclk.hw.vco = -1;
>  }
>  
> +static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> +{
> + int ranges_24[] = { 312000, 552000, 648000 };
> + int ranges_19_38[] = { 307200, 556800, 652800 };
> + int *ranges;
> +
> + switch (ref) {
> + default:
> + MISSING_CASE(ref);
> + case 24000:
> + ranges = ranges_24;
> + break;
> + case 19200:
> + case 38400:
> + ranges = ranges_19_38;
> + break;
> + }
> +
> + if (min_cdclk > ranges[1])
> + return ranges[2];
> + else if (min_cdclk > ranges[0])
> + return ranges[1];
> + else
> + return ranges[0];
> +}
> +
> +static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> +{
> + int ratio;
> +
> + if (cdclk == dev_priv->cdclk.hw.bypass)
> + return 0;
> +
> + switch (cdclk) {
> + default:
> + MISSING_CASE(cdclk);
> + case 307200:
> + case 556800:
> + case 652800:
> + WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> + dev_priv->cdclk.hw.ref != 38400);
> + break;
> + case 312000:
> + case 552000:
> + case 648000:
> + WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> + }
> +
> + ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> +
> + return dev_priv->cdclk.hw.ref * ratio;
> +}
> +
> +static void icl_set_cdclk(struct drm_i915_private *dev_priv,
> +  const struct intel_cdclk_state *cdclk_state)
> +{
> + unsigned int cdclk = cdclk_state->cdclk;
> + unsigned int vco = cdclk_state->vco;
> + int ret;
> +
> + mutex_lock(&dev_priv->pcu_lock);
> + ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> + SKL_CDCLK_PREPARE_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE, 3);
> + mutex_unlock(&dev_priv->pcu_lock);
> + if (ret) {
> + DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
> +  ret);
> + return;
> + }
> +
> + if (dev_priv->cdclk.hw.vco != 0 &&
> +    dev_priv->cdclk.hw.vco != vco)
> + cnl_cdclk_pll_disable(dev_priv);
> +
> + if (dev_priv->cdclk.hw.vco != vco)
> + cnl_cdclk_pll_enable(dev_priv, vco);
> +
> + I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
> +      skl_cdclk_decimal(cdclk));
> +
> + mutex_lock(&dev_priv->pcu_lock);
> + /* TODO: add proper DVFS support. */
> + sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 2);
> + mutex_unlock(&dev_priv->pcu_lock);
> +
> + intel_update_cdclk(dev_priv);
> +}
> +
> +static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> +  struct intel_cdclk_state *cdclk_state)
> +{
> + u32 val;
> +
> + cdclk_state->bypass = 50000;
> +
> + val = I915_READ(SKL_DSSM);
> + switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
> + default:
> + MISSING_CASE(val);
> + case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
> + cdclk_state->ref = 24000;
> + break;
> + case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
> + cdclk_state->ref = 19200;
> + break;
> + case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
> + cdclk_state->ref = 38400;
> + break;
> + }
> +
> + val = I915_READ(BXT_DE_PLL_ENABLE);
> + if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> +    (val & BXT_DE_PLL_LOCK) == 0) {
> + /* CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
> + * setting it to zero is a way to signal that. */

checkpatch throws a warn on this comment:

WARNING: Block comments use a trailing */ on a separate line
#211: FILE: drivers/gpu/drm/i915/intel_cdclk.c:1897:
+                * setting it to zero is a way to signal that. */

total: 0 errors, 1 warnings, 317 lines checked

> + cdclk_state->vco = 0;
> + cdclk_state->cdclk = cdclk_state->bypass;
> + return;
> + }
> +
> + cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
> +
> + val = I915_READ(CDCLK_CTL);
> + WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
> +
> + cdclk_state->cdclk = cdclk_state->vco / 2;
> +}
> +
> +/**
> + * icl_init_cdclk - Initialize CDCLK on ICL
> + * @dev_priv: i915 device
> + *
> + * Initialize CDCLK for ICL. This consists mainly of initializing
> + * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This
> + * is generally done only during the display core initialization sequence, after
> + * which the DMC will take care of turning CDCLK off/on as needed.
> + */
> +void icl_init_cdclk(struct drm_i915_private *dev_priv)
> +{
> + struct intel_cdclk_state sanitized_state;
> + u32 val;
> +
> + /* This sets dev_priv->cdclk.hw. */
> + intel_update_cdclk(dev_priv);
> + intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> +
> + /* This means CDCLK disabled. */
> + if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
> + goto sanitize;
> +
> + val = I915_READ(CDCLK_CTL);
> +
> + if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
> + goto sanitize;
> +
> + if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
> +    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
> + goto sanitize;
> +
> + return;
> +
> +sanitize:
> + DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> +
> + sanitized_state.ref = dev_priv->cdclk.hw.ref;
> + sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
> + sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
> +     sanitized_state.cdclk);
> +
> + icl_set_cdclk(dev_priv, &sanitized_state);
> +}
> +
> +/**
> + * icl_uninit_cdclk - Uninitialize CDCLK on ICL
> + * @dev_priv: i915 device
> + *
> + * Uninitialize CDCLK for ICL. This is done only during the display core
> + * uninitialization sequence.
> + */
> +void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
> +{
> + struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> +
> + cdclk_state.cdclk = cdclk_state.bypass;
> + cdclk_state.vco = 0;
> +
> + icl_set_cdclk(dev_priv, &cdclk_state);
> +}
> +
>  /**
>   * cnl_init_cdclk - Initialize CDCLK on CNL
>   * @dev_priv: i915 device
> @@ -2216,6 +2407,36 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
>   return 0;
>  }
>  
> +static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> + unsigned int ref = intel_state->cdclk.logical.ref;
> + int min_cdclk, cdclk, vco;
> +
> + min_cdclk = intel_compute_min_cdclk(state);
> + if (min_cdclk < 0)
> + return min_cdclk;
> +
> + cdclk = icl_calc_cdclk(min_cdclk, ref);
> + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> +
> + intel_state->cdclk.logical.vco = vco;
> + intel_state->cdclk.logical.cdclk = cdclk;
> +
> + if (!intel_state->active_crtcs) {
> + cdclk = icl_calc_cdclk(0, ref);
> + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> +
> + intel_state->cdclk.actual.vco = vco;
> + intel_state->cdclk.actual.cdclk = cdclk;
> + } else {
> + intel_state->cdclk.actual = intel_state->cdclk.logical;
> + }
> +
> + return 0;
> +}
> +
>  static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>  {
>   int max_cdclk_freq = dev_priv->max_cdclk_freq;
> @@ -2249,7 +2470,12 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>   */
>  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
>  {
> - if (IS_CANNONLAKE(dev_priv)) {
> + if (IS_ICELAKE(dev_priv)) {
> + if (dev_priv->cdclk.hw.ref == 24000)
> + dev_priv->max_cdclk_freq = 648000;
> + else
> + dev_priv->max_cdclk_freq = 652800;
> + } else if (IS_CANNONLAKE(dev_priv)) {
>   dev_priv->max_cdclk_freq = 528000;
>   } else if (IS_GEN9_BC(dev_priv)) {
>   u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> @@ -2473,9 +2699,14 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>   dev_priv->display.set_cdclk = cnl_set_cdclk;
>   dev_priv->display.modeset_calc_cdclk =
>   cnl_modeset_calc_cdclk;
> + } else if (IS_ICELAKE(dev_priv)) {
> + dev_priv->display.set_cdclk = icl_set_cdclk;
> + dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
>   }
>  
> - if (IS_CANNONLAKE(dev_priv))
> + if (IS_ICELAKE(dev_priv))
> + dev_priv->display.get_cdclk = icl_get_cdclk;
> + else if (IS_CANNONLAKE(dev_priv))
>   dev_priv->display.get_cdclk = cnl_get_cdclk;
>   else if (IS_GEN9_BC(dev_priv))
>   dev_priv->display.get_cdclk = skl_get_cdclk;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index d6a808374dfb..cca7ecae5cce 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1403,6 +1403,8 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv);
>  void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
>  void bxt_init_cdclk(struct drm_i915_private *dev_priv);
>  void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
> +void icl_init_cdclk(struct drm_i915_private *dev_priv);
> +void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
>  void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
>  void intel_update_cdclk(struct drm_i915_private *dev_priv);
> --
> 2.14.3
>
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Re: [PATCH 2/6] drm/i915/icl: add the main CDCLK functions

[Paulo Zanoni]

Em Seg, 2018-02-05 às 15:13 -0800, Ausmus, James escreveu:
> On Mon, Feb 05, 2018 at 01:40:42PM -0200, Paulo Zanoni wrote:
> > This commit adds the basic CDCLK functions, but it's still missing
> > pieces of the display initialization sequence.
> > 
> > v2:
> >  - Implement the voltage levels.
> >  - Rebase.
> > v3:
> >  - Adjust to the new "bypass" clock (Imre).
> >  - Call intel_dump_cdclk_state() too.
> >  - Rename a variable to avoid confusion.
> >  - Simplify the DVFS part.
> 
>      ^^^^^^^
> Shouldn't this be something more like
> 
> "Drop DVFS part and replace with a TODO"?
> 
> "Simplify" makes it sound like it's still there, but it's not, unless
> I'm missing something?

We now always set the voltage to maximum (2) instead of picking a
possibly wrong value (due to not considering the DDI clocks), so in a
way we do the DVFS thing, just always with the safest value.

The patch that picks the best value will come later.

> 
> 
> > v4:
> >  - Remove wrong bit definition (James).
> >  - Also drive-by fix the coding style for the register definition
> > we
> >    touched.
> > 
> > Cc: James Ausmus <james.ausmus@intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h    |  35 +++---
> >  drivers/gpu/drm/i915/intel_cdclk.c | 235
> > ++++++++++++++++++++++++++++++++++++-
> >  drivers/gpu/drm/i915/intel_drv.h   |   2 +
> >  3 files changed, 255 insertions(+), 17 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index f6e1677e8211..2b6a908056d6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7182,8 +7182,12 @@ enum {
> >  #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> >  #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> >  
> > -#define SKL_DSSM _MMIO(0x51004)
> > -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> > +#define SKL_DSSM _MMIO(0x51004)
> > +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
> >  
> >  #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
> >  #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
> > @@ -8816,20 +8820,21 @@ enum skl_power_gate {
> >  
> >  /* CDCLK_CTL */
> >  #define CDCLK_CTL _MMIO(0x46000)
> > -#define  CDCLK_FREQ_SEL_MASK (3<<26)
> > -#define  CDCLK_FREQ_450_432 (0<<26)
> > -#define  CDCLK_FREQ_540 (1<<26)
> > -#define  CDCLK_FREQ_337_308 (2<<26)
> > -#define  CDCLK_FREQ_675_617 (3<<26)
> > -#define  BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
> > -#define  BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22)
> > -#define  BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22)
> > -#define  BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
> > -#define  BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
> > -#define  BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20)
> > -#define  CDCLK_DIVMUX_CD_OVERRIDE (1<<19)
> > +#define  CDCLK_FREQ_SEL_MASK (3 << 26)
> > +#define  CDCLK_FREQ_450_432 (0 << 26)
> > +#define  CDCLK_FREQ_540 (1 << 26)
> > +#define  CDCLK_FREQ_337_308 (2 << 26)
> > +#define  CDCLK_FREQ_675_617 (3 << 26)
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22)
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22)
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22)
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22)
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22)
> > +#define  BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
> > +#define  CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
> >  #define  BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
> > -#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
> > +#define  ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
> > +#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
> >  #define  CDCLK_FREQ_DECIMAL_MASK (0x7ff)
> >  
> >  /* LCPLL_CTL */
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index ee788d5be5e3..52a15d0eaae9 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1778,6 +1778,197 @@ static void cnl_sanitize_cdclk(struct
> > drm_i915_private *dev_priv)
> >   dev_priv->cdclk.hw.vco = -1;
> >  }
> >  
> > +static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> > +{
> > + int ranges_24[] = { 312000, 552000, 648000 };
> > + int ranges_19_38[] = { 307200, 556800, 652800 };
> > + int *ranges;
> > +
> > + switch (ref) {
> > + default:
> > + MISSING_CASE(ref);
> > + case 24000:
> > + ranges = ranges_24;
> > + break;
> > + case 19200:
> > + case 38400:
> > + ranges = ranges_19_38;
> > + break;
> > + }
> > +
> > + if (min_cdclk > ranges[1])
> > + return ranges[2];
> > + else if (min_cdclk > ranges[0])
> > + return ranges[1];
> > + else
> > + return ranges[0];
> > +}
> > +
> > +static int icl_calc_cdclk_pll_vco(struct drm_i915_private
> > *dev_priv, int cdclk)
> > +{
> > + int ratio;
> > +
> > + if (cdclk == dev_priv->cdclk.hw.bypass)
> > + return 0;
> > +
> > + switch (cdclk) {
> > + default:
> > + MISSING_CASE(cdclk);
> > + case 307200:
> > + case 556800:
> > + case 652800:
> > + WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> > + dev_priv->cdclk.hw.ref != 38400);
> > + break;
> > + case 312000:
> > + case 552000:
> > + case 648000:
> > + WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> > + }
> > +
> > + ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> > +
> > + return dev_priv->cdclk.hw.ref * ratio;
> > +}
> > +
> > +static void icl_set_cdclk(struct drm_i915_private *dev_priv,
> > +  const struct intel_cdclk_state *cdclk_state)
> > +{
> > + unsigned int cdclk = cdclk_state->cdclk;
> > + unsigned int vco = cdclk_state->vco;
> > + int ret;
> > +
> > + mutex_lock(&dev_priv->pcu_lock);
> > + ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> > + SKL_CDCLK_PREPARE_FOR_CHANGE,
> > + SKL_CDCLK_READY_FOR_CHANGE,
> > + SKL_CDCLK_READY_FOR_CHANGE, 3);
> > + mutex_unlock(&dev_priv->pcu_lock);
> > + if (ret) {
> > + DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
> > +  ret);
> > + return;
> > + }
> > +
> > + if (dev_priv->cdclk.hw.vco != 0 &&
> > +    dev_priv->cdclk.hw.vco != vco)
> > + cnl_cdclk_pll_disable(dev_priv);
> > +
> > + if (dev_priv->cdclk.hw.vco != vco)
> > + cnl_cdclk_pll_enable(dev_priv, vco);
> > +
> > + I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
> > +      skl_cdclk_decimal(cdclk));
> > +
> > + mutex_lock(&dev_priv->pcu_lock);
> > + /* TODO: add proper DVFS support. */
> > + sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 2);
> > + mutex_unlock(&dev_priv->pcu_lock);
> > +
> > + intel_update_cdclk(dev_priv);
> > +}
> > +
> > +static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> > +  struct intel_cdclk_state *cdclk_state)
> > +{
> > + u32 val;
> > +
> > + cdclk_state->bypass = 50000;
> > +
> > + val = I915_READ(SKL_DSSM);
> > + switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
> > + default:
> > + MISSING_CASE(val);
> > + case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
> > + cdclk_state->ref = 24000;
> > + break;
> > + case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
> > + cdclk_state->ref = 19200;
> > + break;
> > + case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
> > + cdclk_state->ref = 38400;
> > + break;
> > + }
> > +
> > + val = I915_READ(BXT_DE_PLL_ENABLE);
> > + if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> > +    (val & BXT_DE_PLL_LOCK) == 0) {
> > + /* CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
> > + * setting it to zero is a way to signal that. */
> 
> checkpatch throws a warn on this comment:
> 
> WARNING: Block comments use a trailing */ on a separate line
> #211: FILE: drivers/gpu/drm/i915/intel_cdclk.c:1897:
> +                * setting it to zero is a way to signal that. */
> 
> total: 0 errors, 1 warnings, 317 lines checked
> 
> > + cdclk_state->vco = 0;
> > + cdclk_state->cdclk = cdclk_state->bypass;
> > + return;
> > + }
> > +
> > + cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state-
> > >ref;
> > +
> > + val = I915_READ(CDCLK_CTL);
> > + WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
> > +
> > + cdclk_state->cdclk = cdclk_state->vco / 2;
> > +}
> > +
> > +/**
> > + * icl_init_cdclk - Initialize CDCLK on ICL
> > + * @dev_priv: i915 device
> > + *
> > + * Initialize CDCLK for ICL. This consists mainly of initializing
> > + * dev_priv->cdclk.hw and sanitizing the state of the hardware if
> > needed. This
> > + * is generally done only during the display core initialization
> > sequence, after
> > + * which the DMC will take care of turning CDCLK off/on as needed.
> > + */
> > +void icl_init_cdclk(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_cdclk_state sanitized_state;
> > + u32 val;
> > +
> > + /* This sets dev_priv->cdclk.hw. */
> > + intel_update_cdclk(dev_priv);
> > + intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> > +
> > + /* This means CDCLK disabled. */
> > + if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
> > + goto sanitize;
> > +
> > + val = I915_READ(CDCLK_CTL);
> > +
> > + if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
> > + goto sanitize;
> > +
> > + if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
> > +    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
> > + goto sanitize;
> > +
> > + return;
> > +
> > +sanitize:
> > + DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> > +
> > + sanitized_state.ref = dev_priv->cdclk.hw.ref;
> > + sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
> > + sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
> > +     sanitized_state.cdclk);
> > +
> > + icl_set_cdclk(dev_priv, &sanitized_state);
> > +}
> > +
> > +/**
> > + * icl_uninit_cdclk - Uninitialize CDCLK on ICL
> > + * @dev_priv: i915 device
> > + *
> > + * Uninitialize CDCLK for ICL. This is done only during the
> > display core
> > + * uninitialization sequence.
> > + */
> > +void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> > +
> > + cdclk_state.cdclk = cdclk_state.bypass;
> > + cdclk_state.vco = 0;
> > +
> > + icl_set_cdclk(dev_priv, &cdclk_state);
> > +}
> > +
> >  /**
> >   * cnl_init_cdclk - Initialize CDCLK on CNL
> >   * @dev_priv: i915 device
> > @@ -2216,6 +2407,36 @@ static int cnl_modeset_calc_cdclk(struct
> > drm_atomic_state *state)
> >   return 0;
> >  }
> >  
> > +static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(state->dev);
> > + struct intel_atomic_state *intel_state =
> > to_intel_atomic_state(state);
> > + unsigned int ref = intel_state->cdclk.logical.ref;
> > + int min_cdclk, cdclk, vco;
> > +
> > + min_cdclk = intel_compute_min_cdclk(state);
> > + if (min_cdclk < 0)
> > + return min_cdclk;
> > +
> > + cdclk = icl_calc_cdclk(min_cdclk, ref);
> > + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> > +
> > + intel_state->cdclk.logical.vco = vco;
> > + intel_state->cdclk.logical.cdclk = cdclk;
> > +
> > + if (!intel_state->active_crtcs) {
> > + cdclk = icl_calc_cdclk(0, ref);
> > + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> > +
> > + intel_state->cdclk.actual.vco = vco;
> > + intel_state->cdclk.actual.cdclk = cdclk;
> > + } else {
> > + intel_state->cdclk.actual = intel_state->cdclk.logical;
> > + }
> > +
> > + return 0;
> > +}
> > +
> >  static int intel_compute_max_dotclk(struct drm_i915_private
> > *dev_priv)
> >  {
> >   int max_cdclk_freq = dev_priv->max_cdclk_freq;
> > @@ -2249,7 +2470,12 @@ static int intel_compute_max_dotclk(struct
> > drm_i915_private *dev_priv)
> >   */
> >  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> >  {
> > - if (IS_CANNONLAKE(dev_priv)) {
> > + if (IS_ICELAKE(dev_priv)) {
> > + if (dev_priv->cdclk.hw.ref == 24000)
> > + dev_priv->max_cdclk_freq = 648000;
> > + else
> > + dev_priv->max_cdclk_freq = 652800;
> > + } else if (IS_CANNONLAKE(dev_priv)) {
> >   dev_priv->max_cdclk_freq = 528000;
> >   } else if (IS_GEN9_BC(dev_priv)) {
> >   u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> > @@ -2473,9 +2699,14 @@ void intel_init_cdclk_hooks(struct
> > drm_i915_private *dev_priv)
> >   dev_priv->display.set_cdclk = cnl_set_cdclk;
> >   dev_priv->display.modeset_calc_cdclk =
> >   cnl_modeset_calc_cdclk;
> > + } else if (IS_ICELAKE(dev_priv)) {
> > + dev_priv->display.set_cdclk = icl_set_cdclk;
> > + dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> >   }
> >  
> > - if (IS_CANNONLAKE(dev_priv))
> > + if (IS_ICELAKE(dev_priv))
> > + dev_priv->display.get_cdclk = icl_get_cdclk;
> > + else if (IS_CANNONLAKE(dev_priv))
> >   dev_priv->display.get_cdclk = cnl_get_cdclk;
> >   else if (IS_GEN9_BC(dev_priv))
> >   dev_priv->display.get_cdclk = skl_get_cdclk;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index d6a808374dfb..cca7ecae5cce 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1403,6 +1403,8 @@ void cnl_init_cdclk(struct drm_i915_private
> > *dev_priv);
> >  void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
> >  void bxt_init_cdclk(struct drm_i915_private *dev_priv);
> >  void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
> > +void icl_init_cdclk(struct drm_i915_private *dev_priv);
> > +void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
> >  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> >  void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> >  void intel_update_cdclk(struct drm_i915_private *dev_priv);
> > --
> > 2.14.3
> > 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/6] drm/i915/icl: add the main CDCLK functions

[Paulo Zanoni]

This commit adds the basic CDCLK functions, but it's still missing
pieces of the display initialization sequence.

v2:
 - Implement the voltage levels.
 - Rebase.
v3:
 - Adjust to the new "bypass" clock (Imre).
 - Call intel_dump_cdclk_state() too.
 - Rename a variable to avoid confusion.
 - Simplify the DVFS part.
v4:
 - Remove wrong bit definition (James).
 - Also drive-by fix the coding style for the register definition we
   touched.
v5:
 - Comment style (checkpatch).

Cc: James Ausmus <james.ausmus@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    |  35 +++---
 drivers/gpu/drm/i915/intel_cdclk.c | 237 ++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h   |   2 +
 3 files changed, 257 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 58057affa133..023ecb844328 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7182,8 +7182,12 @@ enum {
 #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
 #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
 
-#define SKL_DSSM			_MMIO(0x51004)
-#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz	(1 << 31)
+#define SKL_DSSM				_MMIO(0x51004)
+#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK		(7 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz		(0 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz	(1 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz	(2 << 29)
 
 #define GEN7_FF_SLICE_CS_CHICKEN1	_MMIO(0x20e0)
 #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL	(1<<14)
@@ -8816,20 +8820,21 @@ enum skl_power_gate {
 
 /* CDCLK_CTL */
 #define CDCLK_CTL			_MMIO(0x46000)
-#define  CDCLK_FREQ_SEL_MASK		(3<<26)
-#define  CDCLK_FREQ_450_432		(0<<26)
-#define  CDCLK_FREQ_540			(1<<26)
-#define  CDCLK_FREQ_337_308		(2<<26)
-#define  CDCLK_FREQ_675_617		(3<<26)
-#define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_1	(0<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_2	(2<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)
-#define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe)<<20)
-#define  CDCLK_DIVMUX_CD_OVERRIDE	(1<<19)
+#define  CDCLK_FREQ_SEL_MASK		(3 << 26)
+#define  CDCLK_FREQ_450_432		(0 << 26)
+#define  CDCLK_FREQ_540			(1 << 26)
+#define  CDCLK_FREQ_337_308		(2 << 26)
+#define  CDCLK_FREQ_675_617		(3 << 26)
+#define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_1	(0 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_2	(2 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_4	(3 << 22)
+#define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
+#define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
 #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
-#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
+#define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
+#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1 << 16)
 #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
 
 /* LCPLL_CTL */
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index ee788d5be5e3..0256198c7519 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1778,6 +1778,199 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	dev_priv->cdclk.hw.vco = -1;
 }
 
+static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
+{
+	int ranges_24[] = { 312000, 552000, 648000 };
+	int ranges_19_38[] = { 307200, 556800, 652800 };
+	int *ranges;
+
+	switch (ref) {
+	default:
+		MISSING_CASE(ref);
+	case 24000:
+		ranges = ranges_24;
+		break;
+	case 19200:
+	case 38400:
+		ranges = ranges_19_38;
+		break;
+	}
+
+	if (min_cdclk > ranges[1])
+		return ranges[2];
+	else if (min_cdclk > ranges[0])
+		return ranges[1];
+	else
+		return ranges[0];
+}
+
+static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
+{
+	int ratio;
+
+	if (cdclk == dev_priv->cdclk.hw.bypass)
+		return 0;
+
+	switch (cdclk) {
+	default:
+		MISSING_CASE(cdclk);
+	case 307200:
+	case 556800:
+	case 652800:
+		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
+			dev_priv->cdclk.hw.ref != 38400);
+		break;
+	case 312000:
+	case 552000:
+	case 648000:
+		WARN_ON(dev_priv->cdclk.hw.ref != 24000);
+	}
+
+	ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
+
+	return dev_priv->cdclk.hw.ref * ratio;
+}
+
+static void icl_set_cdclk(struct drm_i915_private *dev_priv,
+			  const struct intel_cdclk_state *cdclk_state)
+{
+	unsigned int cdclk = cdclk_state->cdclk;
+	unsigned int vco = cdclk_state->vco;
+	int ret;
+
+	mutex_lock(&dev_priv->pcu_lock);
+	ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+				SKL_CDCLK_PREPARE_FOR_CHANGE,
+				SKL_CDCLK_READY_FOR_CHANGE,
+				SKL_CDCLK_READY_FOR_CHANGE, 3);
+	mutex_unlock(&dev_priv->pcu_lock);
+	if (ret) {
+		DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
+			  ret);
+		return;
+	}
+
+	if (dev_priv->cdclk.hw.vco != 0 &&
+	    dev_priv->cdclk.hw.vco != vco)
+		cnl_cdclk_pll_disable(dev_priv);
+
+	if (dev_priv->cdclk.hw.vco != vco)
+		cnl_cdclk_pll_enable(dev_priv, vco);
+
+	I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
+			      skl_cdclk_decimal(cdclk));
+
+	mutex_lock(&dev_priv->pcu_lock);
+	/* TODO: add proper DVFS support. */
+	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 2);
+	mutex_unlock(&dev_priv->pcu_lock);
+
+	intel_update_cdclk(dev_priv);
+}
+
+static void icl_get_cdclk(struct drm_i915_private *dev_priv,
+			  struct intel_cdclk_state *cdclk_state)
+{
+	u32 val;
+
+	cdclk_state->bypass = 50000;
+
+	val = I915_READ(SKL_DSSM);
+	switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
+	default:
+		MISSING_CASE(val);
+	case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
+		cdclk_state->ref = 24000;
+		break;
+	case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
+		cdclk_state->ref = 19200;
+		break;
+	case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
+		cdclk_state->ref = 38400;
+		break;
+	}
+
+	val = I915_READ(BXT_DE_PLL_ENABLE);
+	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
+	    (val & BXT_DE_PLL_LOCK) == 0) {
+		/*
+		 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
+		 * setting it to zero is a way to signal that.
+		 */
+		cdclk_state->vco = 0;
+		cdclk_state->cdclk = cdclk_state->bypass;
+		return;
+	}
+
+	cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
+
+	val = I915_READ(CDCLK_CTL);
+	WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
+
+	cdclk_state->cdclk = cdclk_state->vco / 2;
+}
+
+/**
+ * icl_init_cdclk - Initialize CDCLK on ICL
+ * @dev_priv: i915 device
+ *
+ * Initialize CDCLK for ICL. This consists mainly of initializing
+ * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This
+ * is generally done only during the display core initialization sequence, after
+ * which the DMC will take care of turning CDCLK off/on as needed.
+ */
+void icl_init_cdclk(struct drm_i915_private *dev_priv)
+{
+	struct intel_cdclk_state sanitized_state;
+	u32 val;
+
+	/* This sets dev_priv->cdclk.hw. */
+	intel_update_cdclk(dev_priv);
+	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
+
+	/* This means CDCLK disabled. */
+	if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
+		goto sanitize;
+
+	val = I915_READ(CDCLK_CTL);
+
+	if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
+		goto sanitize;
+
+	if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
+	    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
+		goto sanitize;
+
+	return;
+
+sanitize:
+	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
+
+	sanitized_state.ref = dev_priv->cdclk.hw.ref;
+	sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
+	sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
+						     sanitized_state.cdclk);
+
+	icl_set_cdclk(dev_priv, &sanitized_state);
+}
+
+/**
+ * icl_uninit_cdclk - Uninitialize CDCLK on ICL
+ * @dev_priv: i915 device
+ *
+ * Uninitialize CDCLK for ICL. This is done only during the display core
+ * uninitialization sequence.
+ */
+void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
+{
+	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
+
+	cdclk_state.cdclk = cdclk_state.bypass;
+	cdclk_state.vco = 0;
+
+	icl_set_cdclk(dev_priv, &cdclk_state);
+}
+
 /**
  * cnl_init_cdclk - Initialize CDCLK on CNL
  * @dev_priv: i915 device
@@ -2216,6 +2409,36 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
 	return 0;
 }
 
+static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->dev);
+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+	unsigned int ref = intel_state->cdclk.logical.ref;
+	int min_cdclk, cdclk, vco;
+
+	min_cdclk = intel_compute_min_cdclk(state);
+	if (min_cdclk < 0)
+		return min_cdclk;
+
+	cdclk = icl_calc_cdclk(min_cdclk, ref);
+	vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
+
+	intel_state->cdclk.logical.vco = vco;
+	intel_state->cdclk.logical.cdclk = cdclk;
+
+	if (!intel_state->active_crtcs) {
+		cdclk = icl_calc_cdclk(0, ref);
+		vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
+
+		intel_state->cdclk.actual.vco = vco;
+		intel_state->cdclk.actual.cdclk = cdclk;
+	} else {
+		intel_state->cdclk.actual = intel_state->cdclk.logical;
+	}
+
+	return 0;
+}
+
 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
 {
 	int max_cdclk_freq = dev_priv->max_cdclk_freq;
@@ -2249,7 +2472,12 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
-	if (IS_CANNONLAKE(dev_priv)) {
+	if (IS_ICELAKE(dev_priv)) {
+		if (dev_priv->cdclk.hw.ref == 24000)
+			dev_priv->max_cdclk_freq = 648000;
+		else
+			dev_priv->max_cdclk_freq = 652800;
+	} else if (IS_CANNONLAKE(dev_priv)) {
 		dev_priv->max_cdclk_freq = 528000;
 	} else if (IS_GEN9_BC(dev_priv)) {
 		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
@@ -2473,9 +2701,14 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.set_cdclk = cnl_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk =
 			cnl_modeset_calc_cdclk;
+	} else if (IS_ICELAKE(dev_priv)) {
+		dev_priv->display.set_cdclk = icl_set_cdclk;
+		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
 	}
 
-	if (IS_CANNONLAKE(dev_priv))
+	if (IS_ICELAKE(dev_priv))
+		dev_priv->display.get_cdclk = icl_get_cdclk;
+	else if (IS_CANNONLAKE(dev_priv))
 		dev_priv->display.get_cdclk = cnl_get_cdclk;
 	else if (IS_GEN9_BC(dev_priv))
 		dev_priv->display.get_cdclk = skl_get_cdclk;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 468ec1e90e16..dcb83b5d88b6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1407,6 +1407,8 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv);
 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
+void icl_init_cdclk(struct drm_i915_private *dev_priv);
+void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
 void intel_update_cdclk(struct drm_i915_private *dev_priv);
-- 
2.14.3

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Re: [PATCH 2/6] drm/i915/icl: add the main CDCLK functions

[James Ausmus]

On Tue, Feb 06, 2018 at 05:33:46PM -0200, Paulo Zanoni wrote:
> This commit adds the basic CDCLK functions, but it's still missing
> pieces of the display initialization sequence.
> 
> v2:
>  - Implement the voltage levels.
>  - Rebase.
> v3:
>  - Adjust to the new "bypass" clock (Imre).
>  - Call intel_dump_cdclk_state() too.
>  - Rename a variable to avoid confusion.
>  - Simplify the DVFS part.
> v4:
>  - Remove wrong bit definition (James).
>  - Also drive-by fix the coding style for the register definition we
>    touched.
> v5:
>  - Comment style (checkpatch).
> 
> Cc: James Ausmus <james.ausmus@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: James Ausmus <james.ausmus@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h    |  35 +++---
>  drivers/gpu/drm/i915/intel_cdclk.c | 237 ++++++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_drv.h   |   2 +
>  3 files changed, 257 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 58057affa133..023ecb844328 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7182,8 +7182,12 @@ enum {
>  #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
>  #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
>  
> -#define SKL_DSSM			_MMIO(0x51004)
> -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz	(1 << 31)
> +#define SKL_DSSM				_MMIO(0x51004)
> +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK		(7 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz		(0 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz	(1 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz	(2 << 29)
>  
>  #define GEN7_FF_SLICE_CS_CHICKEN1	_MMIO(0x20e0)
>  #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL	(1<<14)
> @@ -8816,20 +8820,21 @@ enum skl_power_gate {
>  
>  /* CDCLK_CTL */
>  #define CDCLK_CTL			_MMIO(0x46000)
> -#define  CDCLK_FREQ_SEL_MASK		(3<<26)
> -#define  CDCLK_FREQ_450_432		(0<<26)
> -#define  CDCLK_FREQ_540			(1<<26)
> -#define  CDCLK_FREQ_337_308		(2<<26)
> -#define  CDCLK_FREQ_675_617		(3<<26)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3<<22)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_1	(0<<22)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1<<22)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_2	(2<<22)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)
> -#define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe)<<20)
> -#define  CDCLK_DIVMUX_CD_OVERRIDE	(1<<19)
> +#define  CDCLK_FREQ_SEL_MASK		(3 << 26)
> +#define  CDCLK_FREQ_450_432		(0 << 26)
> +#define  CDCLK_FREQ_540			(1 << 26)
> +#define  CDCLK_FREQ_337_308		(2 << 26)
> +#define  CDCLK_FREQ_675_617		(3 << 26)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3 << 22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_1	(0 << 22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1 << 22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_2	(2 << 22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_4	(3 << 22)
> +#define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
> +#define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
>  #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
> -#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
> +#define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
> +#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1 << 16)
>  #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
>  
>  /* LCPLL_CTL */
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index ee788d5be5e3..0256198c7519 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1778,6 +1778,199 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  	dev_priv->cdclk.hw.vco = -1;
>  }
>  
> +static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> +{
> +	int ranges_24[] = { 312000, 552000, 648000 };
> +	int ranges_19_38[] = { 307200, 556800, 652800 };
> +	int *ranges;
> +
> +	switch (ref) {
> +	default:
> +		MISSING_CASE(ref);
> +	case 24000:
> +		ranges = ranges_24;
> +		break;
> +	case 19200:
> +	case 38400:
> +		ranges = ranges_19_38;
> +		break;
> +	}
> +
> +	if (min_cdclk > ranges[1])
> +		return ranges[2];
> +	else if (min_cdclk > ranges[0])
> +		return ranges[1];
> +	else
> +		return ranges[0];
> +}
> +
> +static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> +{
> +	int ratio;
> +
> +	if (cdclk == dev_priv->cdclk.hw.bypass)
> +		return 0;
> +
> +	switch (cdclk) {
> +	default:
> +		MISSING_CASE(cdclk);
> +	case 307200:
> +	case 556800:
> +	case 652800:
> +		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> +			dev_priv->cdclk.hw.ref != 38400);
> +		break;
> +	case 312000:
> +	case 552000:
> +	case 648000:
> +		WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> +	}
> +
> +	ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> +
> +	return dev_priv->cdclk.hw.ref * ratio;
> +}
> +
> +static void icl_set_cdclk(struct drm_i915_private *dev_priv,
> +			  const struct intel_cdclk_state *cdclk_state)
> +{
> +	unsigned int cdclk = cdclk_state->cdclk;
> +	unsigned int vco = cdclk_state->vco;
> +	int ret;
> +
> +	mutex_lock(&dev_priv->pcu_lock);
> +	ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> +				SKL_CDCLK_PREPARE_FOR_CHANGE,
> +				SKL_CDCLK_READY_FOR_CHANGE,
> +				SKL_CDCLK_READY_FOR_CHANGE, 3);
> +	mutex_unlock(&dev_priv->pcu_lock);
> +	if (ret) {
> +		DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
> +			  ret);
> +		return;
> +	}
> +
> +	if (dev_priv->cdclk.hw.vco != 0 &&
> +	    dev_priv->cdclk.hw.vco != vco)
> +		cnl_cdclk_pll_disable(dev_priv);
> +
> +	if (dev_priv->cdclk.hw.vco != vco)
> +		cnl_cdclk_pll_enable(dev_priv, vco);
> +
> +	I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
> +			      skl_cdclk_decimal(cdclk));
> +
> +	mutex_lock(&dev_priv->pcu_lock);
> +	/* TODO: add proper DVFS support. */
> +	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 2);
> +	mutex_unlock(&dev_priv->pcu_lock);
> +
> +	intel_update_cdclk(dev_priv);
> +}
> +
> +static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> +			  struct intel_cdclk_state *cdclk_state)
> +{
> +	u32 val;
> +
> +	cdclk_state->bypass = 50000;
> +
> +	val = I915_READ(SKL_DSSM);
> +	switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
> +	default:
> +		MISSING_CASE(val);
> +	case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
> +		cdclk_state->ref = 24000;
> +		break;
> +	case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
> +		cdclk_state->ref = 19200;
> +		break;
> +	case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
> +		cdclk_state->ref = 38400;
> +		break;
> +	}
> +
> +	val = I915_READ(BXT_DE_PLL_ENABLE);
> +	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> +	    (val & BXT_DE_PLL_LOCK) == 0) {
> +		/*
> +		 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
> +		 * setting it to zero is a way to signal that.
> +		 */
> +		cdclk_state->vco = 0;
> +		cdclk_state->cdclk = cdclk_state->bypass;
> +		return;
> +	}
> +
> +	cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
> +
> +	val = I915_READ(CDCLK_CTL);
> +	WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
> +
> +	cdclk_state->cdclk = cdclk_state->vco / 2;
> +}
> +
> +/**
> + * icl_init_cdclk - Initialize CDCLK on ICL
> + * @dev_priv: i915 device
> + *
> + * Initialize CDCLK for ICL. This consists mainly of initializing
> + * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This
> + * is generally done only during the display core initialization sequence, after
> + * which the DMC will take care of turning CDCLK off/on as needed.
> + */
> +void icl_init_cdclk(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_cdclk_state sanitized_state;
> +	u32 val;
> +
> +	/* This sets dev_priv->cdclk.hw. */
> +	intel_update_cdclk(dev_priv);
> +	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> +
> +	/* This means CDCLK disabled. */
> +	if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
> +		goto sanitize;
> +
> +	val = I915_READ(CDCLK_CTL);
> +
> +	if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
> +		goto sanitize;
> +
> +	if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
> +	    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
> +		goto sanitize;
> +
> +	return;
> +
> +sanitize:
> +	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> +
> +	sanitized_state.ref = dev_priv->cdclk.hw.ref;
> +	sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
> +	sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
> +						     sanitized_state.cdclk);
> +
> +	icl_set_cdclk(dev_priv, &sanitized_state);
> +}
> +
> +/**
> + * icl_uninit_cdclk - Uninitialize CDCLK on ICL
> + * @dev_priv: i915 device
> + *
> + * Uninitialize CDCLK for ICL. This is done only during the display core
> + * uninitialization sequence.
> + */
> +void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> +
> +	cdclk_state.cdclk = cdclk_state.bypass;
> +	cdclk_state.vco = 0;
> +
> +	icl_set_cdclk(dev_priv, &cdclk_state);
> +}
> +
>  /**
>   * cnl_init_cdclk - Initialize CDCLK on CNL
>   * @dev_priv: i915 device
> @@ -2216,6 +2409,36 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
>  	return 0;
>  }
>  
> +static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->dev);
> +	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> +	unsigned int ref = intel_state->cdclk.logical.ref;
> +	int min_cdclk, cdclk, vco;
> +
> +	min_cdclk = intel_compute_min_cdclk(state);
> +	if (min_cdclk < 0)
> +		return min_cdclk;
> +
> +	cdclk = icl_calc_cdclk(min_cdclk, ref);
> +	vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> +
> +	intel_state->cdclk.logical.vco = vco;
> +	intel_state->cdclk.logical.cdclk = cdclk;
> +
> +	if (!intel_state->active_crtcs) {
> +		cdclk = icl_calc_cdclk(0, ref);
> +		vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> +
> +		intel_state->cdclk.actual.vco = vco;
> +		intel_state->cdclk.actual.cdclk = cdclk;
> +	} else {
> +		intel_state->cdclk.actual = intel_state->cdclk.logical;
> +	}
> +
> +	return 0;
> +}
> +
>  static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>  {
>  	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> @@ -2249,7 +2472,12 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>   */
>  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_CANNONLAKE(dev_priv)) {
> +	if (IS_ICELAKE(dev_priv)) {
> +		if (dev_priv->cdclk.hw.ref == 24000)
> +			dev_priv->max_cdclk_freq = 648000;
> +		else
> +			dev_priv->max_cdclk_freq = 652800;
> +	} else if (IS_CANNONLAKE(dev_priv)) {
>  		dev_priv->max_cdclk_freq = 528000;
>  	} else if (IS_GEN9_BC(dev_priv)) {
>  		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> @@ -2473,9 +2701,14 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  		dev_priv->display.set_cdclk = cnl_set_cdclk;
>  		dev_priv->display.modeset_calc_cdclk =
>  			cnl_modeset_calc_cdclk;
> +	} else if (IS_ICELAKE(dev_priv)) {
> +		dev_priv->display.set_cdclk = icl_set_cdclk;
> +		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
>  	}
>  
> -	if (IS_CANNONLAKE(dev_priv))
> +	if (IS_ICELAKE(dev_priv))
> +		dev_priv->display.get_cdclk = icl_get_cdclk;
> +	else if (IS_CANNONLAKE(dev_priv))
>  		dev_priv->display.get_cdclk = cnl_get_cdclk;
>  	else if (IS_GEN9_BC(dev_priv))
>  		dev_priv->display.get_cdclk = skl_get_cdclk;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 468ec1e90e16..dcb83b5d88b6 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1407,6 +1407,8 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv);
>  void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
>  void bxt_init_cdclk(struct drm_i915_private *dev_priv);
>  void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
> +void icl_init_cdclk(struct drm_i915_private *dev_priv);
> +void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
>  void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
>  void intel_update_cdclk(struct drm_i915_private *dev_priv);
> -- 
> 2.14.3
> 
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[PATCH 3/6] drm/i915/icl: implement the display init/uninit sequences

[Paulo Zanoni]

This code is similar enough to the CNL code that I considered just
adding ICL support to the CNL function, but I think it's still
different enough, and having a function specific to ICL allows us to
more easily adapt code in case the spec changes more later.

We're still missing the power wells and the mbus code, so leave those
pieces with a FIXME comment while they're not here yet.

v2: Don't use _PICK, don't WARN_ON(1), don't forget the chicken bits.
v3: Use _MMIO_PORT() (Ville).

Reviewed-by: James Ausmus <james.ausmus@intel.com> (v2)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 16 ++++++-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 82 ++++++++++++++++++++++++++++++++-
 2 files changed, 94 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2b6a908056d6..9127144337e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1906,6 +1906,11 @@ enum i915_power_well_id {
 #define   CL_POWER_DOWN_ENABLE		(1 << 4)
 #define   SUS_CLOCK_CONFIG		(3 << 0)
 
+#define _ICL_PORT_CL_DW5_A	0x162014
+#define _ICL_PORT_CL_DW5_B	0x6C014
+#define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
+						 _ICL_PORT_CL_DW5_B)
+
 #define _PORT_CL1CM_DW9_A		0x162024
 #define _PORT_CL1CM_DW9_BC		0x6C024
 #define   IREF0RC_OFFSET_SHIFT		8
@@ -7169,8 +7174,9 @@ enum {
 #define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
 
 #define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)
-#define   SKL_SELECT_ALTERNATE_DC_EXIT	(1<<30)
-#define   MASK_WAKEMEM			(1<<13)
+#define   SKL_SELECT_ALTERNATE_DC_EXIT	(1 << 30)
+#define   MASK_WAKEMEM			(1 << 13)
+#define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
 
 #define SKL_DFSM			_MMIO(0x51000)
 #define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
@@ -9743,4 +9749,10 @@ enum skl_power_gate {
 #define  MMCD_PCLA		(1 << 31)
 #define  MMCD_HOTSPOT_EN	(1 << 27)
 
+#define _ICL_PHY_MISC_A		0x64C00
+#define _ICL_PHY_MISC_B		0x64C04
+#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
+						 _ICL_PHY_MISC_B)
+#define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
+
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b4ef7875f055..c432a661bdd3 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2919,6 +2919,80 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
 	I915_WRITE(CHICKEN_MISC_2, val);
 }
 
+static void icl_display_core_init(struct drm_i915_private *dev_priv,
+				  bool resume)
+{
+	enum port port;
+	u32 val;
+
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+	/* 1. Enable PCH reset handshake. */
+	val = I915_READ(HSW_NDE_RSTWRN_OPT);
+	val |= RESET_PCH_HANDSHAKE_ENABLE;
+	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+
+	for (port = PORT_A; port <= PORT_B; port++) {
+		/* 2. Enable DDI combo PHY comp. */
+		val = I915_READ(ICL_PHY_MISC(port));
+		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
+		I915_WRITE(ICL_PHY_MISC(port), val);
+
+		cnl_set_procmon_ref_values(dev_priv, port);
+
+		val = I915_READ(ICL_PORT_COMP_DW0(port));
+		val |= COMP_INIT;
+		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
+
+		/* 3. Set power down enable. */
+		val = I915_READ(ICL_PORT_CL_DW5(port));
+		val |= CL_POWER_DOWN_ENABLE;
+		I915_WRITE(ICL_PORT_CL_DW5(port), val);
+	}
+
+	/* 4. Enable power well 1 (PG1) and aux IO power. */
+	/* FIXME: ICL power wells code not here yet. */
+
+	/* 5. Enable CDCLK. */
+	icl_init_cdclk(dev_priv);
+
+	/* 6. Enable DBUF. */
+	gen9_dbuf_enable(dev_priv);
+
+	/* 7. Setup MBUS. */
+	/* FIXME: MBUS code not here yet. */
+
+	/* 8. CHICKEN_DCPR_1 */
+	I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
+					CNL_DDI_CLOCK_REG_ACCESS_ON);
+}
+
+static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
+{
+	enum port port;
+	u32 val;
+
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+	/* 1. Disable all display engine functions -> aready done */
+
+	/* 2. Disable DBUF */
+	gen9_dbuf_disable(dev_priv);
+
+	/* 3. Disable CD clock */
+	icl_uninit_cdclk(dev_priv);
+
+	/* 4. Disable Power Well 1 (PG1) and Aux IO Power */
+	/* FIXME: ICL power wells code not here yet. */
+
+	/* 5. Disable Comp */
+	for (port = PORT_A; port <= PORT_B; port++) {
+		val = I915_READ(ICL_PHY_MISC(port));
+		val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
+		I915_WRITE(ICL_PHY_MISC(port), val);
+	}
+}
+
 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_well *cmn_bc =
@@ -3051,7 +3125,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
 
 	power_domains->initializing = true;
 
-	if (IS_CANNONLAKE(dev_priv)) {
+	if (IS_ICELAKE(dev_priv)) {
+		icl_display_core_init(dev_priv, resume);
+	} else if (IS_CANNONLAKE(dev_priv)) {
 		cnl_display_core_init(dev_priv, resume);
 	} else if (IS_GEN9_BC(dev_priv)) {
 		skl_display_core_init(dev_priv, resume);
@@ -3092,7 +3168,9 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
 	if (!i915_modparams.disable_power_well)
 		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 
-	if (IS_CANNONLAKE(dev_priv))
+	if (IS_ICELAKE(dev_priv))
+		icl_display_core_uninit(dev_priv);
+	else if (IS_CANNONLAKE(dev_priv))
 		cnl_display_core_uninit(dev_priv);
 	else if (IS_GEN9_BC(dev_priv))
 		skl_display_core_uninit(dev_priv);
-- 
2.14.3

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[PATCH 4/6] drm/i915/icl: Enable both DBuf slices during init

[Paulo Zanoni]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

ICL has 2 slices of DBuf, enable both the slices during display init.

Ideally we should only enable the second slice when needed in order to
save power, but while we're not there yet, adopt the simpler solution
to keep us bug-free.

v2 (from Paulo):
  - Add the TODO comment.
  - Reorganize where things are defined.
  - Fix indentation.
  - Remove unnecessary POSTING_READ() calls.
  - Improve the commit message.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         |  2 ++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 34 +++++++++++++++++++++++++++++++--
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9127144337e1..6ab984c763bf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7165,6 +7165,8 @@ enum {
 #define  DISP_DATA_PARTITION_5_6	(1<<6)
 #define  DISP_IPC_ENABLE		(1<<3)
 #define DBUF_CTL	_MMIO(0x45008)
+#define DBUF_CTL_S1	_MMIO(0x45008)
+#define DBUF_CTL_S2	_MMIO(0x44FE8)
 #define  DBUF_POWER_REQUEST		(1<<31)
 #define  DBUF_POWER_STATE		(1<<30)
 #define GEN7_MSG_CTL	_MMIO(0x45010)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index c432a661bdd3..7e8694a70661 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2646,6 +2646,36 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
 		DRM_ERROR("DBuf power disable timeout!\n");
 }
 
+/*
+ * TODO: we shouldn't always enable DBUF_CTL_S2, we should only enable it when
+ * needed and keep it disabled as much as possible.
+ */
+static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
+{
+	I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
+	I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);
+	POSTING_READ(DBUF_CTL_S2);
+
+	udelay(10);
+
+	if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
+	    !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
+		DRM_ERROR("DBuf power enable timeout\n");
+}
+
+static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
+{
+	I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
+	I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
+	POSTING_READ(DBUF_CTL_S2);
+
+	udelay(10);
+
+	if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
+	    (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
+		DRM_ERROR("DBuf power disable timeout!\n");
+}
+
 static void skl_display_core_init(struct drm_i915_private *dev_priv,
 				   bool resume)
 {
@@ -2957,7 +2987,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
 	icl_init_cdclk(dev_priv);
 
 	/* 6. Enable DBUF. */
-	gen9_dbuf_enable(dev_priv);
+	icl_dbuf_enable(dev_priv);
 
 	/* 7. Setup MBUS. */
 	/* FIXME: MBUS code not here yet. */
@@ -2977,7 +3007,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
 	/* 1. Disable all display engine functions -> aready done */
 
 	/* 2. Disable DBUF */
-	gen9_dbuf_disable(dev_priv);
+	icl_dbuf_disable(dev_priv);
 
 	/* 3. Disable CD clock */
 	icl_uninit_cdclk(dev_priv);
-- 
2.14.3

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[PATCH 5/6] drm/i915/icl: initialize MBus during display init

[Paulo Zanoni]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

This patch initializes MBus during display initialization.

Changes since V2 (from Paulo):
 - Don't forget to remove the WARN_ON(1) call.
Changes since V1:
 - Rebase to use function like Macros

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 7e8694a70661..16790f2576ec 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2676,6 +2676,18 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
 		DRM_ERROR("DBuf power disable timeout!\n");
 }
 
+static void icl_mbus_init(struct drm_i915_private *dev_priv)
+{
+	uint32_t val;
+
+	val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
+	      MBUS_ABOX_BT_CREDIT_POOL2(16) |
+	      MBUS_ABOX_B_CREDIT(1) |
+	      MBUS_ABOX_BW_CREDIT(1);
+
+	I915_WRITE(MBUS_ABOX_CTL, val);
+}
+
 static void skl_display_core_init(struct drm_i915_private *dev_priv,
 				   bool resume)
 {
@@ -2990,7 +3002,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
 	icl_dbuf_enable(dev_priv);
 
 	/* 7. Setup MBUS. */
-	/* FIXME: MBUS code not here yet. */
+	icl_mbus_init(dev_priv);
 
 	/* 8. CHICKEN_DCPR_1 */
 	I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
-- 
2.14.3

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[PATCH 6/6] drm/i915/icl: program mbus during pipe enable

[Paulo Zanoni]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

This patch program default values of MBus credit during pipe enable.

Changes since V2:
 - We don't need to do anything when disabling the pipe
Changes Since V1:
 - Add WARN_ON (Paulo)
 - Remove TODO comment
 - Program 0 during pipe disable
 - Rebase

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ad8d9c6c40e4..c5de5fe4e0dd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5418,6 +5418,23 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
 	I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
 }
 
+static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	uint32_t val;
+
+	if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
+		return;
+
+	val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
+
+	/* Program B credit equally to all pipes */
+	val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
+
+	I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
+}
+
 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 				struct drm_atomic_state *old_state)
 {
@@ -5495,6 +5512,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	if (dev_priv->display.initial_watermarks != NULL)
 		dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
 
+	if (INTEL_GEN(dev_priv) >= 11)
+		icl_pipe_mbus_enable(intel_crtc);
+
 	/* XXX: Do the pipe assertions at the right place for BXT DSI. */
 	if (!transcoder_is_dsi(cpu_transcoder))
 		intel_enable_pipe(pipe_config);
-- 
2.14.3

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Re: [PATCH 6/6] drm/i915/icl: program mbus during pipe enable

[Ville Syrjälä]

On Mon, Feb 05, 2018 at 01:40:46PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
> 
> This patch program default values of MBus credit during pipe enable.
> 
> Changes since V2:
>  - We don't need to do anything when disabling the pipe
> Changes Since V1:
>  - Add WARN_ON (Paulo)
>  - Remove TODO comment
>  - Program 0 during pipe disable
>  - Rebase
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Reviewed-by: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ad8d9c6c40e4..c5de5fe4e0dd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5418,6 +5418,23 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
>  	I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
>  }
>  
> +static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
> +	uint32_t val;
> +
> +	if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
> +		return;

That's clearly impossible. IMO these sort of super paranoid checks
are just adding noise to the code, making it harder to follow as you
may start to question your own sanity on account of not being able
to figure out how it could ever happen.

> +
> +	val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
> +
> +	/* Program B credit equally to all pipes */
> +	val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
> +
> +	I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
> +}
> +
>  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  				struct drm_atomic_state *old_state)
>  {
> @@ -5495,6 +5512,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  	if (dev_priv->display.initial_watermarks != NULL)
>  		dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
>  
> +	if (INTEL_GEN(dev_priv) >= 11)
> +		icl_pipe_mbus_enable(intel_crtc);
> +
>  	/* XXX: Do the pipe assertions at the right place for BXT DSI. */
>  	if (!transcoder_is_dsi(cpu_transcoder))
>  		intel_enable_pipe(pipe_config);
> -- 
> 2.14.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[PATCH 6/6] drm/i915/icl: program mbus during pipe enable

[Paulo Zanoni]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

This patch program default values of MBus credit during pipe enable.

Changes Since V1:
 - Add WARN_ON (Paulo)
 - Remove TODO comment
 - Program 0 during pipe disable
 - Rebase
Changes since V2:
 - We don't need to do anything when disabling the pipe
Changes since V3 (from Paulo):
 - Remove WARN() that we'll never be able to trigger (Ville).

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ad8d9c6c40e4..5a75bc1eafbc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5418,6 +5418,20 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
 	I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
 }
 
+static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	uint32_t val;
+
+	val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
+
+	/* Program B credit equally to all pipes */
+	val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
+
+	I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
+}
+
 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 				struct drm_atomic_state *old_state)
 {
@@ -5495,6 +5509,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	if (dev_priv->display.initial_watermarks != NULL)
 		dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
 
+	if (INTEL_GEN(dev_priv) >= 11)
+		icl_pipe_mbus_enable(intel_crtc);
+
 	/* XXX: Do the pipe assertions at the right place for BXT DSI. */
 	if (!transcoder_is_dsi(cpu_transcoder))
 		intel_enable_pipe(pipe_config);
-- 
2.14.3

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✗ Fi.CI.BAT: warning for ICL display initialization, selected patches

[Patchwork]

== Series Details ==

Series: ICL display initialization, selected patches
URL   : https://patchwork.freedesktop.org/series/37668/
State : warning

== Summary ==

Series 37668v1 ICL display initialization, selected patches
https://patchwork.freedesktop.org/api/1.0/series/37668/revisions/1/mbox/

Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                pass       -> FAIL       (fi-gdg-551) fdo#102575
Test gem_sync:
        Subgroup basic-all:
                pass       -> SKIP       (fi-pnv-d510)
        Subgroup basic-each:
                pass       -> SKIP       (fi-pnv-d510)
        Subgroup basic-many-each:
                pass       -> SKIP       (fi-pnv-d510)
        Subgroup basic-store-all:
                pass       -> SKIP       (fi-pnv-d510)
        Subgroup basic-store-each:
                pass       -> SKIP       (fi-pnv-d510)
Test gem_tiled_blits:
        Subgroup basic:
                pass       -> SKIP       (fi-pnv-d510)
Test gem_tiled_fence_blits:
        Subgroup basic:
                pass       -> SKIP       (fi-pnv-d510)
Test gem_wait:
        Subgroup basic-busy-all:
                pass       -> SKIP       (fi-pnv-d510)
        Subgroup basic-wait-all:
                pass       -> SKIP       (fi-pnv-d510)
        Subgroup basic-await-all:
                pass       -> SKIP       (fi-pnv-d510)
Test kms_busy:
        Subgroup basic-flip-a:
                pass       -> SKIP       (fi-pnv-d510)
        Subgroup basic-flip-b:
                pass       -> SKIP       (fi-pnv-d510)
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-legacy:
                pass       -> SKIP       (fi-pnv-d510)
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713
                dmesg-warn -> PASS       (fi-cnl-y3) fdo#104951

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:417s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:424s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:372s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:486s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:281s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:481s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:485s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:464s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:449s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:567s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:578s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:413s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:281s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:510s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:395s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:397s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:409s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:449s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:418s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:456s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:494s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:452s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:501s
fi-pnv-d510      total:288  pass:209  dwarn:1   dfail:0   fail:0   skip:78  time:549s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:429s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:504s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:529s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:486s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:483s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:423s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:428s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:526s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:400s
Blacklisted hosts:
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:468s

ff0257f786f370890f8fa940b2cd7dce0064be72 drm-tip: 2018y-02m-05d-13h-26m-33s UTC integration manifest
2086d3c36965 drm/i915/icl: program mbus during pipe enable
ed4dde5d7a81 drm/i915/icl: initialize MBus during display init
c71622366d96 drm/i915/icl: Enable both DBuf slices during init
c12ae377f9d4 drm/i915/icl: implement the display init/uninit sequences
c759c21841a0 drm/i915/icl: add the main CDCLK functions
dda77601603d drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7889/issues.html
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✗ Fi.CI.BAT: failure for ICL display initialization, selected patches (rev2)

[Patchwork]

== Series Details ==

Series: ICL display initialization, selected patches (rev2)
URL   : https://patchwork.freedesktop.org/series/37668/
State : failure

== Summary ==

Series 37668v2 ICL display initialization, selected patches
https://patchwork.freedesktop.org/api/1.0/series/37668/revisions/2/mbox/

Test kms_frontbuffer_tracking:
        Subgroup basic:
                fail       -> PASS       (fi-cnl-y3)
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                pass       -> DMESG-WARN (fi-elk-e7500)
        Subgroup suspend-read-crc-pipe-c:
                skip       -> INCOMPLETE (fi-elk-e7500)

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:415s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:421s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:372s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:482s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:281s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:480s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:486s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:468s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:454s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:571s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:586s
fi-elk-e7500     total:246  pass:193  dwarn:1   dfail:0   fail:0   skip:51 
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:278s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:516s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:388s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:397s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:411s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:452s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:412s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:455s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:497s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:452s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:500s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:579s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:436s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:504s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:526s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:481s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:488s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:413s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:429s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:522s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:394s
Blacklisted hosts:
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:469s

3a4afd6dae3d932908ea929f18b935e709430846 drm-tip: 2018y-02m-05d-17h-02m-56s UTC integration manifest
902617c197e5 drm/i915/icl: program mbus during pipe enable
c3d31e5dd607 drm/i915/icl: initialize MBus during display init
dfc05050a954 drm/i915/icl: Enable both DBuf slices during init
415b27d6b35d drm/i915/icl: implement the display init/uninit sequences
f4428ca16d5a drm/i915/icl: add the main CDCLK functions
9a4dcbd9b7ac drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7891/issues.html
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✗ Fi.CI.BAT: warning for ICL display initialization, selected patches (rev3)

[Patchwork]

== Series Details ==

Series: ICL display initialization, selected patches (rev3)
URL   : https://patchwork.freedesktop.org/series/37668/
State : warning

== Summary ==

Series 37668v3 ICL display initialization, selected patches
https://patchwork.freedesktop.org/api/1.0/series/37668/revisions/3/mbox/

Test gem_sync:
        Subgroup basic-all:
                pass       -> SKIP       (fi-pnv-d510)
        Subgroup basic-each:
                pass       -> SKIP       (fi-pnv-d510)
        Subgroup basic-many-each:
                pass       -> SKIP       (fi-pnv-d510)
        Subgroup basic-store-all:
                pass       -> SKIP       (fi-pnv-d510)
        Subgroup basic-store-each:
                pass       -> SKIP       (fi-pnv-d510)
Test gem_tiled_blits:
        Subgroup basic:
                pass       -> SKIP       (fi-pnv-d510)
Test gem_tiled_fence_blits:
        Subgroup basic:
                pass       -> SKIP       (fi-pnv-d510)
Test gem_wait:
        Subgroup basic-busy-all:
                pass       -> SKIP       (fi-pnv-d510)
        Subgroup basic-wait-all:
                pass       -> SKIP       (fi-pnv-d510)
        Subgroup basic-await-all:
                pass       -> SKIP       (fi-pnv-d510)
Test kms_busy:
        Subgroup basic-flip-a:
                pass       -> SKIP       (fi-pnv-d510)
        Subgroup basic-flip-b:
                pass       -> SKIP       (fi-pnv-d510)
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-legacy:
                pass       -> SKIP       (fi-pnv-d510)
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                pass       -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:417s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:421s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:374s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:480s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:481s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:484s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:468s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:453s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:563s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:576s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:413s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:288s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:511s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:389s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:400s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:412s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:456s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:416s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:455s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:493s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:455s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:498s
fi-pnv-d510      total:288  pass:209  dwarn:1   dfail:0   fail:0   skip:78  time:566s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:429s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:504s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:530s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:490s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:468s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:415s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:427s
fi-snb-2520m     total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:401s
Blacklisted hosts:
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:467s

078873da383505cf8d6940229007115b31f1d5e0 drm-tip: 2018y-02m-06d-11h-21m-36s UTC integration manifest
bc7626231687 drm/i915/icl: program mbus during pipe enable
c5685a5e3c0a drm/i915/icl: initialize MBus during display init
1e49c3e1a31d drm/i915/icl: Enable both DBuf slices during init
997836294f3f drm/i915/icl: implement the display init/uninit sequences
efca4ab50db7 drm/i915/icl: add the main CDCLK functions
6156b26e5f4f drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7913/issues.html
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Re: ✗ Fi.CI.BAT: warning for ICL display initialization, selected patches (rev3)

[Paulo Zanoni]

Em Ter, 2018-02-06 às 19:54 +0000, Patchwork escreveu:
> == Series Details ==
> 
> Series: ICL display initialization, selected patches (rev3)
> URL   : https://patchwork.freedesktop.org/series/37668/
> State : warning
> 
> == Summary ==
> 
> Series 37668v3 ICL display initialization, selected patches
> https://patchwork.freedesktop.org/api/1.0/series/37668/revisions/3/mb
> ox/
> 
> Test gem_sync:
>         Subgroup basic-all:
>                 pass       -> SKIP       (fi-pnv-d510)
>         Subgroup basic-each:
>                 pass       -> SKIP       (fi-pnv-d510)
>         Subgroup basic-many-each:
>                 pass       -> SKIP       (fi-pnv-d510)
>         Subgroup basic-store-all:
>                 pass       -> SKIP       (fi-pnv-d510)
>         Subgroup basic-store-each:
>                 pass       -> SKIP       (fi-pnv-d510)
> Test gem_tiled_blits:
>         Subgroup basic:
>                 pass       -> SKIP       (fi-pnv-d510)
> Test gem_tiled_fence_blits:
>         Subgroup basic:
>                 pass       -> SKIP       (fi-pnv-d510)
> Test gem_wait:
>         Subgroup basic-busy-all:
>                 pass       -> SKIP       (fi-pnv-d510)
>         Subgroup basic-wait-all:
>                 pass       -> SKIP       (fi-pnv-d510)
>         Subgroup basic-await-all:
>                 pass       -> SKIP       (fi-pnv-d510)
> Test kms_busy:
>         Subgroup basic-flip-a:
>                 pass       -> SKIP       (fi-pnv-d510)
>         Subgroup basic-flip-b:
>                 pass       -> SKIP       (fi-pnv-d510)
> Test kms_cursor_legacy:
>         Subgroup basic-busy-flip-before-cursor-legacy:
>                 pass       -> SKIP       (fi-pnv-d510)

IGT-Version: 1.21-g3fd9b578 (x86_64) (Linux: 4.15.0-CI-Patchwork_7913+
x86_64)
Test requirement not met in function igt_require_gem, file
ioctl_wrappers.c:1441:
Test requirement: err == 0
Unresponsive i915/GEM device
Last errno: 5, Input/output error
Subtest basic-all: SKIP

The fact that these SKIPs don't happen in the test of rev2 and the
changes from both rev1->rev2 and rev2->rev3 are not related to pnv at
all suggests that these skips are unrelated to this series.

A small search on the other recent CI results points me to lots of
patches resulting in a SKIP -> pass for this test, with some others
doing the opposite. Perhaps we could signal this a a bug in the CI
results.


> Test kms_pipe_crc_basic:
>         Subgroup suspend-read-crc-pipe-b:
>                 pass       -> INCOMPLETE (fi-snb-2520m) fdo#103713
> 
> fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
> 
> fi-bdw-
> 5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
> time:417s
> fi-bdw-
> gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
> time:421s
> fi-blb-
> e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
> time:374s
> fi-bsw-
> n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
> time:480s
> fi-bxt-
> dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
> time:481s
> fi-bxt-
> j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
> time:484s
> fi-byt-
> j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
> time:468s
> fi-byt-
> n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
> time:453s
> fi-cfl-
> s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
> time:563s
> fi-cnl-
> y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
> time:576s
> fi-elk-
> e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
> time:413s
> fi-gdg-
> 551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108
> time:288s
> fi-glk-
> 1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
> time:511s
> fi-hsw-
> 4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
> time:389s
> fi-hsw-
> 4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
> time:400s
> fi-ilk-
> 650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
> time:412s
> fi-ivb-
> 3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
> time:456s
> fi-ivb-
> 3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
> time:416s
> fi-kbl-
> 7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
> time:455s
> fi-kbl-
> 7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
> time:493s
> fi-kbl-
> 7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
> time:455s
> fi-kbl-
> r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
> time:498s
> fi-pnv-
> d510      total:288  pass:209  dwarn:1   dfail:0   fail:0   skip:78  
> time:566s
> fi-skl-
> 6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
> time:429s
> fi-skl-
> 6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
> time:504s
> fi-skl-
> 6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
> time:530s
> fi-skl-
> 6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
> time:490s
> fi-skl-
> 6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
> time:468s
> fi-skl-
> guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
> time:415s
> fi-skl-
> gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
> time:427s
> fi-snb-
> 2520m     total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
> fi-snb-
> 2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
> time:401s
> Blacklisted hosts:
> fi-glk-
> dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
> time:467s
> 
> 078873da383505cf8d6940229007115b31f1d5e0 drm-tip: 2018y-02m-06d-11h-
> 21m-36s UTC integration manifest
> bc7626231687 drm/i915/icl: program mbus during pipe enable
> c5685a5e3c0a drm/i915/icl: initialize MBus during display init
> 1e49c3e1a31d drm/i915/icl: Enable both DBuf slices during init
> 997836294f3f drm/i915/icl: implement the display init/uninit
> sequences
> efca4ab50db7 drm/i915/icl: add the main CDCLK functions
> 6156b26e5f4f drm/i915/icl: add ICL support to
> cnl_set_procmon_ref_values
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchw
> ork_7913/issues.html
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Re: ✗ Fi.CI.BAT: warning for ICL display initialization, selected patches (rev3)

[Tomi Sarvela]

On 02/08/18 15:34, Paulo Zanoni wrote:
> Em Ter, 2018-02-06 às 19:54 +0000, Patchwork escreveu:
>> == Series Details ==
>>
>> Series: ICL display initialization, selected patches (rev3)
>> URL   : https://patchwork.freedesktop.org/series/37668/
>> State : warning
>>
>> == Summary ==
>>
>> Series 37668v3 ICL display initialization, selected patches
>> https://patchwork.freedesktop.org/api/1.0/series/37668/revisions/3/mb
>> ox/
>>
>> Test gem_sync:
>>          Subgroup basic-all:
>>                  pass       -> SKIP       (fi-pnv-d510)
>>          Subgroup basic-each:
>>                  pass       -> SKIP       (fi-pnv-d510)
>>          Subgroup basic-many-each:
>>                  pass       -> SKIP       (fi-pnv-d510)
>>          Subgroup basic-store-all:
>>                  pass       -> SKIP       (fi-pnv-d510)
>>          Subgroup basic-store-each:
>>                  pass       -> SKIP       (fi-pnv-d510)
> 
> IGT-Version: 1.21-g3fd9b578 (x86_64) (Linux: 4.15.0-CI-Patchwork_7913+
> x86_64)

> 
> The fact that these SKIPs don't happen in the test of rev2 and the
> changes from both rev1->rev2 and rev2->rev3 are not related to pnv at
> all suggests that these skips are unrelated to this series.
> 
> A small search on the other recent CI results points me to lots of
> patches resulting in a SKIP -> pass for this test, with some others
> doing the opposite. Perhaps we could signal this a a bug in the CI
> results.

Result flipflops are handled through cibuglog which connects (test,host) 
to fd.o bug. There is no bug for PNV for this issue, it's quite rare as 
can be seen from

https://intel-gfx-ci.01.org/tree/drm-tip/fi-pnv-d510.html

(the bug seem to appear after failure on gem_ringfill@basic-default-hang)

So yes: in this case CI gives misleading result, but that can be easily 
checked (by human) from history. Work is being done towards cibuglog-ng 
that is much easier to use to detect and create bugs like this, and has 
better knowledge about previous runs.

Tomi
-- 
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
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