From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Fam Zheng" <famz@redhat.com>,
qemu-devel@nongnu.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Alistair Francis" <alistair.francis@xilinx.com>,
"open list:Xilinx Zynq" <qemu-arm@nongnu.org>
Subject: [Qemu-arm] [PATCH v13 16/30] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet
Date: Tue, 13 Feb 2018 01:07:55 -0300 [thread overview]
Message-ID: <20180213040809.26021-17-f4bug@amsat.org> (raw)
In-Reply-To: <20180213040809.26021-1-f4bug@amsat.org>
checking Xilinx datasheet "UG585" (v1.12.1)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/arm/xilinx_zynq.c | 53 ++++++++++++++++++++++++++++------------------------
tests/sdhci-test.c | 5 +++++
2 files changed, 34 insertions(+), 24 deletions(-)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 1836a4ed45..0f76333770 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -61,6 +61,8 @@ static const int dma_irqs[8] = {
#define SLCR_XILINX_UNLOCK_KEY 0xdf0d
#define SLCR_XILINX_LOCK_KEY 0x767b
+#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
+
#define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
extract32((x), 12, 4) << 16)
@@ -165,10 +167,8 @@ static void zynq_init(MachineState *machine)
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
- DeviceState *dev, *carddev;
+ DeviceState *dev;
SysBusDevice *busdev;
- DriveInfo *di;
- BlockBackend *blk;
qemu_irq pic[64];
int n;
@@ -247,27 +247,32 @@ static void zynq_init(MachineState *machine)
gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
- dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
- qdev_init_nofail(dev);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000);
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]);
-
- di = drive_get_next(IF_SD);
- blk = di ? blk_by_legacy_dinfo(di) : NULL;
- carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
- qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
-
- dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
- qdev_init_nofail(dev);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
-
- di = drive_get_next(IF_SD);
- blk = di ? blk_by_legacy_dinfo(di) : NULL;
- carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
- qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
+ for (n = 0; n < 2; n++) {
+ int hci_irq = n ? 79 : 56;
+ hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
+ DriveInfo *di;
+ BlockBackend *blk;
+ DeviceState *carddev;
+
+ /* Compatible with:
+ * - SD Host Controller Specification Version 2.0 Part A2
+ * - SDIO Specification Version 2.0
+ * - MMC Specification Version 3.31
+ */
+ dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
+ qdev_prop_set_uint8(dev, "sd-spec-version", 2);
+ qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
+
+ di = drive_get_next(IF_SD);
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
+ carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
+ object_property_set_bool(OBJECT(carddev), true, "realized",
+ &error_fatal);
+ }
dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
qdev_init_nofail(dev);
diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c
index 24feea744a..898c43ff4f 100644
--- a/tests/sdhci-test.c
+++ b/tests/sdhci-test.c
@@ -41,6 +41,11 @@ static const struct sdhci_t {
/* Exynos4210 */
{ "arm", "smdkc210",
{0x12510000, 2, 0, {1, 0x5e80080} } },
+
+ /* Zynq-7000 */
+ { "arm", "xilinx-zynq-a9", /* Datasheet: UG585 (v1.12.1) */
+ {0xe0100000, 2, 0, {1, 0x69ec0080} } },
+
};
typedef struct QSDHCI {
--
2.16.1
WARNING: multiple messages have this Message-ID (diff)
From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
qemu-devel@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
"Alistair Francis" <alistair.francis@xilinx.com>,
"Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
"Fam Zheng" <famz@redhat.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"open list:Xilinx Zynq" <qemu-arm@nongnu.org>
Subject: [Qemu-devel] [PATCH v13 16/30] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet
Date: Tue, 13 Feb 2018 01:07:55 -0300 [thread overview]
Message-ID: <20180213040809.26021-17-f4bug@amsat.org> (raw)
In-Reply-To: <20180213040809.26021-1-f4bug@amsat.org>
checking Xilinx datasheet "UG585" (v1.12.1)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/arm/xilinx_zynq.c | 53 ++++++++++++++++++++++++++++------------------------
tests/sdhci-test.c | 5 +++++
2 files changed, 34 insertions(+), 24 deletions(-)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 1836a4ed45..0f76333770 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -61,6 +61,8 @@ static const int dma_irqs[8] = {
#define SLCR_XILINX_UNLOCK_KEY 0xdf0d
#define SLCR_XILINX_LOCK_KEY 0x767b
+#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
+
#define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
extract32((x), 12, 4) << 16)
@@ -165,10 +167,8 @@ static void zynq_init(MachineState *machine)
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
- DeviceState *dev, *carddev;
+ DeviceState *dev;
SysBusDevice *busdev;
- DriveInfo *di;
- BlockBackend *blk;
qemu_irq pic[64];
int n;
@@ -247,27 +247,32 @@ static void zynq_init(MachineState *machine)
gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
- dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
- qdev_init_nofail(dev);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000);
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]);
-
- di = drive_get_next(IF_SD);
- blk = di ? blk_by_legacy_dinfo(di) : NULL;
- carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
- qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
-
- dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
- qdev_init_nofail(dev);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
-
- di = drive_get_next(IF_SD);
- blk = di ? blk_by_legacy_dinfo(di) : NULL;
- carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
- qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
+ for (n = 0; n < 2; n++) {
+ int hci_irq = n ? 79 : 56;
+ hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
+ DriveInfo *di;
+ BlockBackend *blk;
+ DeviceState *carddev;
+
+ /* Compatible with:
+ * - SD Host Controller Specification Version 2.0 Part A2
+ * - SDIO Specification Version 2.0
+ * - MMC Specification Version 3.31
+ */
+ dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
+ qdev_prop_set_uint8(dev, "sd-spec-version", 2);
+ qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
+
+ di = drive_get_next(IF_SD);
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
+ carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
+ object_property_set_bool(OBJECT(carddev), true, "realized",
+ &error_fatal);
+ }
dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
qdev_init_nofail(dev);
diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c
index 24feea744a..898c43ff4f 100644
--- a/tests/sdhci-test.c
+++ b/tests/sdhci-test.c
@@ -41,6 +41,11 @@ static const struct sdhci_t {
/* Exynos4210 */
{ "arm", "smdkc210",
{0x12510000, 2, 0, {1, 0x5e80080} } },
+
+ /* Zynq-7000 */
+ { "arm", "xilinx-zynq-a9", /* Datasheet: UG585 (v1.12.1) */
+ {0xe0100000, 2, 0, {1, 0x69ec0080} } },
+
};
typedef struct QSDHCI {
--
2.16.1
next prev parent reply other threads:[~2018-02-13 4:19 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-13 4:07 [Qemu-devel] [PATCH v13 00/30] SDHCI: clean v1/2 Specs, UHS-I cards tuning sequence Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 01/30] sdhci: use error_propagate(local_err) in realize() Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 02/30] sdhci: add qtest to check the SD capabilities register Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 03/30] sdhci: add check_capab_readonly() qtest Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 04/30] sdhci: add a check_capab_baseclock() qtest Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 05/30] sdhci: add a check_capab_sdma() qtest Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 06/30] sdhci: add qtest to check the SD Spec version Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 07/30] sdhci: add a 'spec_version property' (default to v2) Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 08/30] sdhci: use a numeric value for the default CAPAB register Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 09/30] sdhci: simplify sdhci_get_fifolen() Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 10/30] sdhci: check the Spec v1 capabilities correctness Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 12/30] sdhci: Fix 64-bit ADMA2 Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 14/30] hw/arm/exynos4210: access the 64-bit capareg with qdev_prop_set_uint64() Philippe Mathieu-Daudé
2018-02-13 4:07 ` Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 15/30] hw/arm/exynos4210: add a comment about a very similar SDHCI (Spec. v2) Philippe Mathieu-Daudé
2018-02-13 4:07 ` Philippe Mathieu-Daudé
2018-02-13 4:07 ` Philippe Mathieu-Daudé [this message]
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 16/30] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 18/30] sdhci: rename the hostctl1 register Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 19/30] sdhci: implement the Host Control 2 register (tuning sequence) Philippe Mathieu-Daudé
2018-02-13 4:07 ` [Qemu-devel] [PATCH v13 20/30] sdbus: add trace events Philippe Mathieu-Daudé
2018-04-27 11:55 ` Peter Maydell
2018-04-30 13:49 ` Edgar E. Iglesias
2018-05-01 3:35 ` Philippe Mathieu-Daudé
2018-05-01 9:03 ` Peter Maydell
2018-05-04 16:11 ` Philippe Mathieu-Daudé
2018-05-04 16:18 ` Peter Maydell
2018-02-13 4:08 ` [Qemu-devel] [PATCH v13 21/30] sdhci: implement UHS-I voltage switch Philippe Mathieu-Daudé
2018-02-13 4:08 ` [Qemu-devel] [PATCH v13 22/30] sdhci: implement CMD/DAT[] fields in the Present State register Philippe Mathieu-Daudé
2018-02-13 4:08 ` [Qemu-devel] [PATCH v13 23/30] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3 Philippe Mathieu-Daudé
2018-02-13 4:08 ` Philippe Mathieu-Daudé
2018-02-13 4:08 ` [Qemu-devel] [PATCH v13 24/30] hw/arm/bcm2835_peripherals: change maximum block size to 1kB Philippe Mathieu-Daudé
2018-02-13 4:08 ` Philippe Mathieu-Daudé
2018-02-13 4:08 ` [Qemu-devel] [PATCH v13 25/30] hw/arm/fsl-imx6: implement SDHCI Spec. v3 Philippe Mathieu-Daudé
2018-02-13 4:08 ` Philippe Mathieu-Daudé
2018-02-13 4:08 ` [Qemu-devel] [PATCH v13 26/30] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet Philippe Mathieu-Daudé
2018-02-13 4:08 ` Philippe Mathieu-Daudé
2018-02-13 4:08 ` [Qemu-devel] [PATCH v13 27/30] hw/arm/xilinx_zynqmp: enable the UHS-I mode Philippe Mathieu-Daudé
2018-02-13 4:08 ` Philippe Mathieu-Daudé
2018-02-13 4:08 ` [Qemu-devel] [PATCH v13 28/30] sdhci: check Spec v3 capabilities qtest Philippe Mathieu-Daudé
2018-02-13 4:08 ` [Qemu-devel] [PATCH v13 29/30] sdhci: add a check_capab_v3() qtest Philippe Mathieu-Daudé
2018-02-13 4:08 ` [Qemu-devel] [PATCH v13 30/30] sdhci: add Spec v4.2 register definitions Philippe Mathieu-Daudé
2018-02-15 22:46 ` Alistair Francis
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