From: Will Deacon <will.deacon@arm.com>
To: Shanker Donthineni <shankerd@codeaurora.org>
Cc: Philip Elcan <pelcan@codeaurora.org>,
Marc Zyngier <marc.zyngier@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
linux-kernel <linux-kernel@vger.kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
kvmarm <kvmarm@lists.cs.columbia.edu>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC
Date: Wed, 7 Mar 2018 10:04:20 +0000 [thread overview]
Message-ID: <20180307100419.GA9111@arm.com> (raw)
In-Reply-To: <dbc6e162-d245-a685-8bfe-f506d18e19e3@codeaurora.org>
On Tue, Mar 06, 2018 at 01:33:00PM -0600, Shanker Donthineni wrote:
> > I also confirmed with Thomas Speier, we can skip __flush_icache_all() if DIC=1.
Thanks,
> Planning to patch __flush_icache_all() itself instead of changing the callers. This
> way we can avoid "ic ialluis" completely. Is this okay for you?
>
> static inline void __flush_icache_all(void)
> {
> /* Instruction cache invalidation is not required for I/D coherence? */
> if (!cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) {
> asm("ic ialluis");
> dsb(ish);
> }
> }
Yup, that's what I meant, cheers.
Will
WARNING: multiple messages have this Message-ID (diff)
From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC
Date: Wed, 7 Mar 2018 10:04:20 +0000 [thread overview]
Message-ID: <20180307100419.GA9111@arm.com> (raw)
In-Reply-To: <dbc6e162-d245-a685-8bfe-f506d18e19e3@codeaurora.org>
On Tue, Mar 06, 2018 at 01:33:00PM -0600, Shanker Donthineni wrote:
> > I also confirmed with Thomas Speier, we can skip __flush_icache_all() if DIC=1.
Thanks,
> Planning to patch __flush_icache_all() itself instead of changing the callers. This
> way we can avoid "ic ialluis" completely. Is this okay for you?
>
> static inline void __flush_icache_all(void)
> {
> /* Instruction cache invalidation is not required for I/D coherence? */
> if (!cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) {
> asm("ic ialluis");
> dsb(ish);
> }
> }
Yup, that's what I meant, cheers.
Will
next prev parent reply other threads:[~2018-03-07 10:04 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-01 4:14 [PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC Shanker Donthineni
2018-03-01 4:14 ` Shanker Donthineni
2018-03-06 13:44 ` Will Deacon
2018-03-06 13:44 ` Will Deacon
2018-03-06 14:47 ` Shanker Donthineni
2018-03-06 14:47 ` Shanker Donthineni
2018-03-06 15:23 ` Will Deacon
2018-03-06 15:23 ` Will Deacon
2018-03-06 18:48 ` Shanker Donthineni
2018-03-06 18:48 ` Shanker Donthineni
2018-03-06 19:33 ` Shanker Donthineni
2018-03-06 19:33 ` Shanker Donthineni
2018-03-07 10:04 ` Will Deacon [this message]
2018-03-07 10:04 ` Will Deacon
2018-03-06 13:52 ` Robin Murphy
2018-03-06 13:52 ` Robin Murphy
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