From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V2] arm64: tlbflush: avoid writing RES0 bits
Date: Wed, 28 Mar 2018 12:58:04 +0100 [thread overview]
Message-ID: <20180328115804.GD30850@arm.com> (raw)
In-Reply-To: <96f894bb-4855-a77f-3fd1-c8a2878faabb@codeaurora.org>
On Tue, Mar 27, 2018 at 08:03:07PM -0500, Shanker Donthineni wrote:
> On 03/27/2018 12:36 PM, Will Deacon wrote:
> > On Tue, Mar 27, 2018 at 09:53:16AM -0500, Shanker Donthineni wrote:
> >>>> @@ -154,8 +163,8 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
> >>>> ????????? return;
> >>>> ????? }
> >>>> ? -??? start = asid | (start >> 12);
> >>>> -??? end = asid | (end >> 12);
> >>>> +??? start = __TLBI_VADDR(start, asid);
> >>>> +??? end = __TLBI_VADDR(end, asid);
> >
> > Can you test this bit too, please? ;)
> >
>
> I've verified the basic boot functionality on QDF2400 platform. But I can see now
> after your comments, it leads to TLB conflicts because of ASID is truncated to zero
> due to two times 48bit shift.
>
> Thanks for catching this one.
I just noticed it during review. In general, if you're making changes
relating to virtual memory stuff I'd *strongly* advise you to do more
than a basic boot test. It's amazing how much appears to run fine when
stuff like TLB invalidation is completely broken.
Anyway, thanks for turning around a new version so quickly.
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Shanker Donthineni <shankerd@codeaurora.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Philip Elcan <pelcan@codeaurora.org>,
Catalin Marinas <catalin.marinas@arm.com>,
linux-kernel@vger.kernel.org,
Thomas Speier <tspeier@codeaurora.org>,
Robin Murphy <robin.murphy@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V2] arm64: tlbflush: avoid writing RES0 bits
Date: Wed, 28 Mar 2018 12:58:04 +0100 [thread overview]
Message-ID: <20180328115804.GD30850@arm.com> (raw)
In-Reply-To: <96f894bb-4855-a77f-3fd1-c8a2878faabb@codeaurora.org>
On Tue, Mar 27, 2018 at 08:03:07PM -0500, Shanker Donthineni wrote:
> On 03/27/2018 12:36 PM, Will Deacon wrote:
> > On Tue, Mar 27, 2018 at 09:53:16AM -0500, Shanker Donthineni wrote:
> >>>> @@ -154,8 +163,8 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
> >>>> return;
> >>>> }
> >>>> - start = asid | (start >> 12);
> >>>> - end = asid | (end >> 12);
> >>>> + start = __TLBI_VADDR(start, asid);
> >>>> + end = __TLBI_VADDR(end, asid);
> >
> > Can you test this bit too, please? ;)
> >
>
> I've verified the basic boot functionality on QDF2400 platform. But I can see now
> after your comments, it leads to TLB conflicts because of ASID is truncated to zero
> due to two times 48bit shift.
>
> Thanks for catching this one.
I just noticed it during review. In general, if you're making changes
relating to virtual memory stuff I'd *strongly* advise you to do more
than a basic boot test. It's amazing how much appears to run fine when
stuff like TLB invalidation is completely broken.
Anyway, thanks for turning around a new version so quickly.
Will
next prev parent reply other threads:[~2018-03-28 11:58 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-27 3:21 [PATCH V2] arm64: tlbflush: avoid writing RES0 bits Philip Elcan
2018-03-27 3:21 ` Philip Elcan
2018-03-27 11:34 ` Robin Murphy
2018-03-27 11:34 ` Robin Murphy
2018-03-27 14:53 ` Shanker Donthineni
2018-03-27 14:53 ` Shanker Donthineni
2018-03-27 17:36 ` Will Deacon
2018-03-27 17:36 ` Will Deacon
2018-03-28 1:03 ` Shanker Donthineni
2018-03-28 1:03 ` Shanker Donthineni
2018-03-28 1:08 ` Philip Elcan
2018-03-28 1:08 ` Philip Elcan
2018-03-28 11:58 ` Will Deacon [this message]
2018-03-28 11:58 ` Will Deacon
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