From: Tvrtko Ursulin <tursulin@ursulin.net>
To: igt-dev@lists.freedesktop.org
Cc: Intel-gfx@lists.freedesktop.org,
Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Subject: [igt-dev] [PATCH i-g-t v2 2/2] tests/gem_eio: Add reset and unwedge stress testing
Date: Tue, 3 Apr 2018 12:36:44 +0100 [thread overview]
Message-ID: <20180403113644.6855-1-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20180329130528.8302-2-tvrtko.ursulin@linux.intel.com>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reset and unwedge stress testing is supposed to trigger wedging or resets
at incovenient times and then re-use the context so either the context or
driver tracking might get confused and break.
v2:
* Renamed for more sensible naming.
* Added some comments to explain what the test is doing. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
tests/gem_eio.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index b7c5047f0816..9599e73db736 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -591,6 +591,74 @@ static void test_inflight_internal(int fd, unsigned int wait)
close(fd);
}
+/*
+ * Verify that we can submit and execute work after unwedging the GPU.
+ */
+static void test_reset_stress(int fd, unsigned int flags)
+{
+ uint32_t ctx0 = gem_context_create(fd);
+
+ igt_until_timeout(5) {
+ struct drm_i915_gem_execbuffer2 execbuf = { };
+ struct drm_i915_gem_exec_object2 obj = { };
+ uint32_t bbe = MI_BATCH_BUFFER_END;
+ igt_spin_t *hang;
+ unsigned int i;
+ uint32_t ctx;
+
+ gem_quiescent_gpu(fd);
+
+ igt_require(i915_reset_control(flags & TEST_WEDGE ?
+ false : true));
+
+ ctx = context_create_safe(fd);
+
+ /*
+ * Start executing a spin batch with some queued batches
+ * against a different context after it.
+ */
+ hang = spin_sync(fd, ctx0, 0);
+
+ obj.handle = gem_create(fd, 4096);
+ gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
+
+ execbuf.buffers_ptr = to_user_pointer(&obj);
+ execbuf.buffer_count = 1;
+ execbuf.rsvd1 = ctx0;
+
+ for (i = 0; i < 10; i++)
+ gem_execbuf(fd, &execbuf);
+
+ /* Wedge after a small delay. */
+ igt_assert_eq(__check_wait(fd, obj.handle, 100e3), 0);
+
+ /* Unwedge by forcing a reset. */
+ igt_assert(i915_reset_control(true));
+ trigger_reset(fd);
+
+ gem_quiescent_gpu(fd);
+
+ /*
+ * Verify that we are able to submit work after unwedging from
+ * both contexts.
+ */
+ execbuf.rsvd1 = ctx;
+ for (i = 0; i < 5; i++)
+ gem_execbuf(fd, &execbuf);
+
+ execbuf.rsvd1 = ctx0;
+ for (i = 0; i < 5; i++)
+ gem_execbuf(fd, &execbuf);
+
+ gem_sync(fd, obj.handle);
+ igt_spin_batch_free(fd, hang);
+ gem_context_destroy(fd, ctx);
+ gem_close(fd, obj.handle);
+ }
+
+ gem_context_destroy(fd, ctx0);
+}
+
static int fd = -1;
static void
@@ -635,6 +703,12 @@ igt_main
igt_subtest("in-flight-suspend")
test_inflight_suspend(fd);
+ igt_subtest("reset-stress")
+ test_reset_stress(fd, 0);
+
+ igt_subtest("unwedge-stress")
+ test_reset_stress(fd, TEST_WEDGE);
+
igt_subtest_group {
const struct {
unsigned int wait;
--
2.14.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
WARNING: multiple messages have this Message-ID (diff)
From: Tvrtko Ursulin <tursulin@ursulin.net>
To: igt-dev@lists.freedesktop.org
Cc: Intel-gfx@lists.freedesktop.org
Subject: [PATCH i-g-t v2 2/2] tests/gem_eio: Add reset and unwedge stress testing
Date: Tue, 3 Apr 2018 12:36:44 +0100 [thread overview]
Message-ID: <20180403113644.6855-1-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20180329130528.8302-2-tvrtko.ursulin@linux.intel.com>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reset and unwedge stress testing is supposed to trigger wedging or resets
at incovenient times and then re-use the context so either the context or
driver tracking might get confused and break.
v2:
* Renamed for more sensible naming.
* Added some comments to explain what the test is doing. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
tests/gem_eio.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index b7c5047f0816..9599e73db736 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -591,6 +591,74 @@ static void test_inflight_internal(int fd, unsigned int wait)
close(fd);
}
+/*
+ * Verify that we can submit and execute work after unwedging the GPU.
+ */
+static void test_reset_stress(int fd, unsigned int flags)
+{
+ uint32_t ctx0 = gem_context_create(fd);
+
+ igt_until_timeout(5) {
+ struct drm_i915_gem_execbuffer2 execbuf = { };
+ struct drm_i915_gem_exec_object2 obj = { };
+ uint32_t bbe = MI_BATCH_BUFFER_END;
+ igt_spin_t *hang;
+ unsigned int i;
+ uint32_t ctx;
+
+ gem_quiescent_gpu(fd);
+
+ igt_require(i915_reset_control(flags & TEST_WEDGE ?
+ false : true));
+
+ ctx = context_create_safe(fd);
+
+ /*
+ * Start executing a spin batch with some queued batches
+ * against a different context after it.
+ */
+ hang = spin_sync(fd, ctx0, 0);
+
+ obj.handle = gem_create(fd, 4096);
+ gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
+
+ execbuf.buffers_ptr = to_user_pointer(&obj);
+ execbuf.buffer_count = 1;
+ execbuf.rsvd1 = ctx0;
+
+ for (i = 0; i < 10; i++)
+ gem_execbuf(fd, &execbuf);
+
+ /* Wedge after a small delay. */
+ igt_assert_eq(__check_wait(fd, obj.handle, 100e3), 0);
+
+ /* Unwedge by forcing a reset. */
+ igt_assert(i915_reset_control(true));
+ trigger_reset(fd);
+
+ gem_quiescent_gpu(fd);
+
+ /*
+ * Verify that we are able to submit work after unwedging from
+ * both contexts.
+ */
+ execbuf.rsvd1 = ctx;
+ for (i = 0; i < 5; i++)
+ gem_execbuf(fd, &execbuf);
+
+ execbuf.rsvd1 = ctx0;
+ for (i = 0; i < 5; i++)
+ gem_execbuf(fd, &execbuf);
+
+ gem_sync(fd, obj.handle);
+ igt_spin_batch_free(fd, hang);
+ gem_context_destroy(fd, ctx);
+ gem_close(fd, obj.handle);
+ }
+
+ gem_context_destroy(fd, ctx0);
+}
+
static int fd = -1;
static void
@@ -635,6 +703,12 @@ igt_main
igt_subtest("in-flight-suspend")
test_inflight_suspend(fd);
+ igt_subtest("reset-stress")
+ test_reset_stress(fd, 0);
+
+ igt_subtest("unwedge-stress")
+ test_reset_stress(fd, TEST_WEDGE);
+
igt_subtest_group {
const struct {
unsigned int wait;
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2018-04-03 11:36 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-29 13:05 [igt-dev] [PATCH i-g-t v2 1/2] tests/gem_eio: Never re-use contexts which were in the middle of GPU reset Tvrtko Ursulin
2018-03-29 13:05 ` Tvrtko Ursulin
2018-03-29 13:05 ` [igt-dev] [PATCH i-g-t 2/2] tests/gem_eio: Add context destroyer test Tvrtko Ursulin
2018-03-29 13:05 ` Tvrtko Ursulin
2018-04-03 11:36 ` Tvrtko Ursulin [this message]
2018-04-03 11:36 ` [PATCH i-g-t v2 2/2] tests/gem_eio: Add reset and unwedge stress testing Tvrtko Ursulin
2018-04-03 11:51 ` [Intel-gfx] " Chris Wilson
2018-04-03 11:51 ` Chris Wilson
2018-04-03 18:24 ` [igt-dev] " Antonio Argenziano
2018-04-03 18:24 ` Antonio Argenziano
2018-04-03 18:34 ` Antonio Argenziano
2018-04-03 18:34 ` Antonio Argenziano
2018-04-04 9:58 ` [Intel-gfx] " Tvrtko Ursulin
2018-04-04 9:58 ` Tvrtko Ursulin
2018-04-04 10:06 ` [Intel-gfx] " Chris Wilson
2018-04-04 10:06 ` Chris Wilson
2018-04-04 16:54 ` [Intel-gfx] " Antonio Argenziano
2018-04-04 16:54 ` Antonio Argenziano
2018-03-29 17:50 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,v2,1/2] tests/gem_eio: Never re-use contexts which were in the middle of GPU reset Patchwork
2018-03-29 22:14 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2018-04-03 13:39 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,v2,1/2] tests/gem_eio: Never re-use contexts which were in the middle of GPU reset (rev2) Patchwork
2018-04-03 15:26 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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