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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [PATCH v4 06/10] [PATCH v4 6/9] Linux Patch #6
Date: Wed, 25 Apr 2018 12:12:14 -0400	[thread overview]
Message-ID: <20180425161214.GD27641@localhost.localdomain> (raw)
In-Reply-To: <20180424163656.GI15235@pd.tnic>

On Tue, Apr 24, 2018 at 06:36:56PM +0200, speck for Borislav Petkov wrote:
> On Tue, Apr 24, 2018 at 11:46:53AM -0400, speck for Konrad Rzeszutek Wilk wrote:
> > You OK with it moving the nicely aligned ( 7*32.. and so on?): It will
> > look like this:
> > 
> > 215 #define X86_FEATURE_USE_IBPB            ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
> > 216 #define X86_FEATURE_USE_IBRS_FW         ( 7*32+22) /* "" Use IBRS during runtime firmware calls */
> > 217 #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */
> > 218 
> 
> Yeah, Ingo will have to realign them again :-)
> 
> > Right, which on Intel can also be guarded by X86_FEATURE_RDS and on AMD
> > it was implicit by the families (15h->17h). (The v4, patch #7 has that
> > logic). The v2 (or v1.7) of the posting had the logic you just described but
> > with different names.
> 
> So I'd like for us to use a single one - either X86_FEATURE_RDS or
> X86_FEATURE_SPEC_STORE_BYPASS_DISABLE globally. No need to cause
> unnecessary confusion with two things meaning roughly the same thing.

This is the part that won't work (sorry about not spotting this
earlier).

That is X86_FEATURE_RDS gets sets on Intel when we slurp up
CPUID_7_EDX:
 789         /* Additional Intel-defined flags: level 0x00000007 */
 790         if (c->cpuid_level >= 0x00000007) {
 791                 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
 792                 c->x86_capability[CPUID_7_0_EBX] = ebx;
 793                 c->x86_capability[CPUID_7_ECX] = ecx;
 794                 c->x86_capability[CPUID_7_EDX] = edx;
 795         }

From there on Intel we have the 'rds' flag already set.

Which means that the logic in Intel code, as you suggested:

688         if (cpu_has(c, X86_FEATURE_RDS))
689                 x86_set_spec_ctrl(SPEC_CTRL_RDS);

will always do its thing.

Unless in bugs.c we end up clearing the RDS flag:

459         if (mode == SPEC_STORE_BYPASS_NONE)
460                 setup_clear_cpu_cap(X86_FEATURE_RDS);
461         else {
462                 if (boot_cpu_has(X86_FEATURE_RDS))
463                         x86_spec_ctrl_base |= SPEC_CTRL_RDS;
464
465         }

?

  parent reply	other threads:[~2018-04-25 16:12 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-24  3:16 [MODERATED] [PATCH v4 06/10] [PATCH v4 6/9] Linux Patch #6 konrad.wilk
2018-04-24 13:21 ` [MODERATED] " Borislav Petkov
2018-04-24 15:13   ` Linus Torvalds
2018-04-24 15:46   ` Konrad Rzeszutek Wilk
2018-04-24 16:36     ` Borislav Petkov
2018-04-24 18:07       ` Konrad Rzeszutek Wilk
2018-04-24 18:46         ` Borislav Petkov
2018-04-25 15:32           ` Konrad Rzeszutek Wilk
2018-04-25 17:25             ` Borislav Petkov
2018-04-25 16:12       ` Konrad Rzeszutek Wilk [this message]
2018-04-25 16:19         ` Konrad Rzeszutek Wilk
2018-04-25 17:29           ` Borislav Petkov
2018-04-25 17:26         ` Borislav Petkov
2018-04-25 16:51 ` Tim Chen
2018-04-25 17:38   ` Konrad Rzeszutek Wilk
2018-04-25 20:25     ` Tim Chen

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