[MODERATED] Re: [PATCH v4 06/10] [PATCH v4 6/9] Linux Patch #6

[Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>]

On Wed, Apr 25, 2018 at 09:51:52AM -0700, speck for Tim Chen wrote:
> 
> Future Intel CPUs that do not have speculative store bypass vulnerability will
> turn on bit 4 in MSR 0x10a (MSR_IA32_ARCH_CAPABILITIES).


Is it going to be called 'RDS' or SSB'?

I am going to assume ARCH_CAP_RDS_NO

> 
> So we should add this check.
> 
> Suggested code changes below.

Let me roll it in (removed the {} in the cpu_set_bug_bits).

> 
> Tim
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 96ae1e7..c28af75 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -69,6 +69,7 @@
>  #define MSR_IA32_ARCH_CAPABILITIES	0x0000010a
>  #define ARCH_CAP_RDCL_NO		(1 << 0)   /* Not susceptible to Meltdown */
>  #define ARCH_CAP_IBRS_ALL		(1 << 1)   /* Enhanced IBRS support */
> +#define ARCH_CAP_SSB_NO			(1 << 4)   /* Not susceptible to speculative store bypass */
>  
>  #define MSR_IA32_BBL_CR_CTL		0x00000119
>  #define MSR_IA32_BBL_CR_CTL3		0x0000011e
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index 581eb04..de7fb75 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -944,8 +944,13 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
>  {
>  	u64 ia32_cap = 0;
>  
> -	if (!x86_match_cpu(cpu_no_spec_store_bypass))
> +	if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
> +		rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
> +
> +	if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
> +	    !(ia32_cap & ARCH_CAP_SSB_NO)) {
>  		setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
> +	}
>  
>  	if (x86_match_cpu(cpu_no_speculation))
>  		return;
> @@ -956,9 +961,6 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
>  	if (x86_match_cpu(cpu_no_meltdown))
>  		return;
>  
> -	if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
> -		rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
> -
>  	/* Rogue Data Cache Load? No! */
>  	if (ia32_cap & ARCH_CAP_RDCL_NO)
>  		return;
> -- 
> 2.7.4
>