* [PATCH 1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper
@ 2018-05-04 22:17 matthew.s.atwood
2018-05-04 22:18 ` [PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4 matthew.s.atwood
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: matthew.s.atwood @ 2018-05-04 22:17 UTC (permalink / raw)
To: intel-gfx, dri-devel, rodrigo.vivi, jani.nikula, manasi.d.navare,
bleung, alexander.deucher
From: Matt Atwood <matthew.s.atwood@intel.com>
As more differentation occurs between DP spec. Its useful to have these
as macros in a drm_dp_helper.
v2: DPCD_REV_XX to DP_DPCD_REV_XX
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
include/drm/drm_dp_helper.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 91c9bcd4196f..96dcef479ed6 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -64,6 +64,11 @@
/* AUX CH addresses */
/* DPCD */
#define DP_DPCD_REV 0x000
+# define DP_DPCD_REV_10 0x10
+# define DP_DPCD_REV_11 0x11
+# define DP_DPCD_REV_12 0x12
+# define DP_DPCD_REV_13 0x13
+# define DP_DPCD_REV_14 0x14
#define DP_MAX_LINK_RATE 0x001
--
2.17.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4
2018-05-04 22:17 [PATCH 1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper matthew.s.atwood
@ 2018-05-04 22:18 ` matthew.s.atwood
2018-05-08 19:27 ` Rodrigo Vivi
2018-05-04 22:36 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper Patchwork
` (4 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: matthew.s.atwood @ 2018-05-04 22:18 UTC (permalink / raw)
To: intel-gfx, dri-devel, rodrigo.vivi, jani.nikula, manasi.d.navare,
bleung, alexander.deucher
From: Matt Atwood <matthew.s.atwood@intel.com>
DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8
bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended
receiver capabilities. For panels that use this new feature wait interval
would be increased by 512 ms, when spec is max 16 ms. This behavior is
described in table 2-158 of DP 1.4 spec address 0000eh.
With the introduction of DP 1.4 spec main link clock recovery was
standardized to 100 us regardless of TRAINING_AUX_RD_INTERVAL value.
To avoid breaking panels that are not spec compiant we now warn on
invalid values.
V2: commit title/message, masking all 7 bits, warn on out of spec values.
V3: commit message, make link train clock recovery follow DP 1.4 spec.
V4: style changes
V5: typo
V6: print statement revisions, DP_REV to DPCD_REV, comment correction
V7: typo
V8: Style
V9: Strip out DPCD_REV_XX into seperate patch
v10: DPCD_REV_XX to DP_DPCD_REV_XX
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 22 ++++++++++++++++++----
include/drm/drm_dp_helper.h | 1 +
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index ffe14ec3e7f2..36c7609a4bd5 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -119,18 +119,32 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
- if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
+ int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+ DP_TRAINING_AUX_RD_MASK;
+
+ if (rd_interval > 4)
+ DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",
+ rd_interval);
+
+ if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
udelay(100);
else
- mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+ mdelay(rd_interval * 4);
}
EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
- if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
+ int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+ DP_TRAINING_AUX_RD_MASK;
+
+ if (rd_interval > 4)
+ DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",
+ rd_interval);
+
+ if (rd_interval == 0)
udelay(400);
else
- mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+ mdelay(rd_interval * 4);
}
EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 96dcef479ed6..ecf3e2bf293b 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -124,6 +124,7 @@
# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
+# define DP_TRAINING_AUX_RD_MASK 0x7F /* XXX 1.2? */
#define DP_ADAPTER_CAP 0x00f /* 1.2 */
# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
--
2.17.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4
2018-05-04 22:18 ` [PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4 matthew.s.atwood
@ 2018-05-08 19:27 ` Rodrigo Vivi
0 siblings, 0 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2018-05-08 19:27 UTC (permalink / raw)
To: matthew.s.atwood; +Cc: jani.nikula, intel-gfx, dri-devel, alexander.deucher
On Fri, May 04, 2018 at 03:18:00PM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
>
> DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8
> bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended
> receiver capabilities. For panels that use this new feature wait interval
> would be increased by 512 ms, when spec is max 16 ms. This behavior is
> described in table 2-158 of DP 1.4 spec address 0000eh.
>
> With the introduction of DP 1.4 spec main link clock recovery was
> standardized to 100 us regardless of TRAINING_AUX_RD_INTERVAL value.
>
> To avoid breaking panels that are not spec compiant we now warn on
> invalid values.
>
> V2: commit title/message, masking all 7 bits, warn on out of spec values.
> V3: commit message, make link train clock recovery follow DP 1.4 spec.
> V4: style changes
> V5: typo
> V6: print statement revisions, DP_REV to DPCD_REV, comment correction
> V7: typo
> V8: Style
> V9: Strip out DPCD_REV_XX into seperate patch
> v10: DPCD_REV_XX to DP_DPCD_REV_XX
>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
patches pushed to drm-misc-next.
Thanks,
Rodrigo.
> ---
> drivers/gpu/drm/drm_dp_helper.c | 22 ++++++++++++++++++----
> include/drm/drm_dp_helper.h | 1 +
> 2 files changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index ffe14ec3e7f2..36c7609a4bd5 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -119,18 +119,32 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
> EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
>
> void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
> - if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
> + int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> + DP_TRAINING_AUX_RD_MASK;
> +
> + if (rd_interval > 4)
> + DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",
> + rd_interval);
> +
> + if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
> udelay(100);
> else
> - mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
> + mdelay(rd_interval * 4);
> }
> EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
>
> void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
> - if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
> + int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> + DP_TRAINING_AUX_RD_MASK;
> +
> + if (rd_interval > 4)
> + DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",
> + rd_interval);
> +
> + if (rd_interval == 0)
> udelay(400);
> else
> - mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
> + mdelay(rd_interval * 4);
> }
> EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 96dcef479ed6..ecf3e2bf293b 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -124,6 +124,7 @@
> # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
>
> #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
> +# define DP_TRAINING_AUX_RD_MASK 0x7F /* XXX 1.2? */
>
> #define DP_ADAPTER_CAP 0x00f /* 1.2 */
> # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
> --
> 2.17.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper
2018-05-04 22:17 [PATCH 1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper matthew.s.atwood
2018-05-04 22:18 ` [PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4 matthew.s.atwood
@ 2018-05-04 22:36 ` Patchwork
2018-05-04 22:56 ` ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-05-04 22:36 UTC (permalink / raw)
To: matthew.s.atwood; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper
URL : https://patchwork.freedesktop.org/series/42710/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
57a92512db6b drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper
94f073af5236 drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4
-:26: WARNING:TYPO_SPELLING: 'seperate' may be misspelled - perhaps 'separate'?
#26:
V9: Strip out DPCD_REV_XX into seperate patch
total: 0 errors, 1 warnings, 0 checks, 43 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper
2018-05-04 22:17 [PATCH 1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper matthew.s.atwood
2018-05-04 22:18 ` [PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4 matthew.s.atwood
2018-05-04 22:36 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper Patchwork
@ 2018-05-04 22:56 ` Patchwork
2018-05-04 23:43 ` ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-05-04 22:56 UTC (permalink / raw)
To: matthew.s.atwood; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper
URL : https://patchwork.freedesktop.org/series/42710/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4149 -> Patchwork_8912 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42710/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_8912 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_exec_suspend@basic-s3:
fi-ivb-3520m: PASS -> DMESG-WARN (fdo#106084)
==== Possible fixes ====
igt@debugfs_test@read_all_entries:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
igt@gem_exec_suspend@basic-s4-devices:
fi-skl-guc: FAIL (fdo#105900, fdo#104699) -> PASS +1
igt@gem_mmap_gtt@basic-small-bo-tiledx:
fi-gdg-551: FAIL (fdo#102575) -> PASS
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-cnl-psr: FAIL (fdo#100368) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-ivb-3520m: DMESG-WARN (fdo#106084) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104699 https://bugs.freedesktop.org/show_bug.cgi?id=104699
fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900
fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084
== Participating hosts (40 -> 35) ==
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-cnl-y3 fi-hsw-peppy fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4149 -> Patchwork_8912
CI_DRM_4149: 6c2ec0dee7d19b798a1de1101175f5a076549cd9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4461: f772d9a910130b3aec8efa4f09ed723618fae656 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8912: 94f073af523647eea169b3e9a3f91422581f46e5 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4461: 55207ea5154dfaa6d2c128124c50e3be4f9b6440 @ git://anongit.freedesktop.org/piglit
== Linux commits ==
94f073af5236 drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4
57a92512db6b drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8912/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper
2018-05-04 22:17 [PATCH 1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper matthew.s.atwood
` (2 preceding siblings ...)
2018-05-04 22:56 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-05-04 23:43 ` Patchwork
2018-05-08 7:01 ` [PATCH 1/2] " Rodrigo Vivi
2018-05-22 22:59 ` Benson Leung
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-05-04 23:43 UTC (permalink / raw)
To: matthew.s.atwood; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper
URL : https://patchwork.freedesktop.org/series/42710/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4149_full -> Patchwork_8912_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_8912_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_8912_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42710/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_8912_full:
=== IGT changes ===
==== Warnings ====
igt@gem_mocs_settings@mocs-rc6-blt:
shard-kbl: PASS -> SKIP
igt@gem_mocs_settings@mocs-rc6-bsd1:
shard-kbl: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_8912_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_atomic_interruptible@legacy-cursor:
shard-kbl: PASS -> DMESG-WARN (fdo#103313, fdo#105602, fdo#103558) +12
igt@kms_cursor_crc@cursor-256x256-dpms:
shard-apl: PASS -> FAIL (fdo#103232, fdo#104645)
igt@kms_flip@basic-flip-vs-wf_vblank:
shard-hsw: PASS -> FAIL (fdo#103928)
igt@kms_flip@modeset-vs-vblank-race:
shard-hsw: PASS -> FAIL (fdo#103060) +1
igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt:
shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103558) +4
igt@kms_sysfs_edid_timing:
shard-apl: PASS -> WARN (fdo#100047)
igt@kms_vblank@pipe-c-accuracy-idle:
shard-hsw: PASS -> FAIL (fdo#102583)
igt@kms_vblank@pipe-c-ts-continuation-suspend:
shard-kbl: PASS -> INCOMPLETE (fdo#103665) +1
igt@pm_rpm@legacy-planes-dpms:
shard-kbl: PASS -> DMESG-WARN (fdo#103313, fdo#103558)
igt@pm_rpm@system-suspend-modeset:
shard-kbl: PASS -> DMESG-WARN (fdo#103841)
==== Possible fixes ====
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-kbl: INCOMPLETE (fdo#106023, fdo#103665) -> PASS
igt@kms_flip@absolute-wf_vblank-interruptible:
shard-glk: FAIL (fdo#106087) -> PASS
igt@prime_vgem@basic-fence-flip:
shard-kbl: DMESG-WARN (fdo#106247) -> PASS
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#104645 https://bugs.freedesktop.org/show_bug.cgi?id=104645
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#106087 https://bugs.freedesktop.org/show_bug.cgi?id=106087
fdo#106247 https://bugs.freedesktop.org/show_bug.cgi?id=106247
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4149 -> Patchwork_8912
CI_DRM_4149: 6c2ec0dee7d19b798a1de1101175f5a076549cd9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4461: f772d9a910130b3aec8efa4f09ed723618fae656 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8912: 94f073af523647eea169b3e9a3f91422581f46e5 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4461: 55207ea5154dfaa6d2c128124c50e3be4f9b6440 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8912/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper
2018-05-04 22:17 [PATCH 1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper matthew.s.atwood
` (3 preceding siblings ...)
2018-05-04 23:43 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-05-08 7:01 ` Rodrigo Vivi
2018-05-22 22:59 ` Benson Leung
5 siblings, 0 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2018-05-08 7:01 UTC (permalink / raw)
To: matthew.s.atwood; +Cc: jani.nikula, intel-gfx, dri-devel, alexander.deucher
On Fri, May 04, 2018 at 03:17:59PM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
>
> As more differentation occurs between DP spec. Its useful to have these
> as macros in a drm_dp_helper.
>
> v2: DPCD_REV_XX to DP_DPCD_REV_XX
>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> include/drm/drm_dp_helper.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 91c9bcd4196f..96dcef479ed6 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -64,6 +64,11 @@
> /* AUX CH addresses */
> /* DPCD */
> #define DP_DPCD_REV 0x000
> +# define DP_DPCD_REV_10 0x10
> +# define DP_DPCD_REV_11 0x11
> +# define DP_DPCD_REV_12 0x12
> +# define DP_DPCD_REV_13 0x13
> +# define DP_DPCD_REV_14 0x14
>
> #define DP_MAX_LINK_RATE 0x001
>
> --
> 2.17.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper
2018-05-04 22:17 [PATCH 1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper matthew.s.atwood
` (4 preceding siblings ...)
2018-05-08 7:01 ` [PATCH 1/2] " Rodrigo Vivi
@ 2018-05-22 22:59 ` Benson Leung
5 siblings, 0 replies; 9+ messages in thread
From: Benson Leung @ 2018-05-22 22:59 UTC (permalink / raw)
To: matthew.s.atwood
Cc: jani.nikula, intel-gfx, dri-devel, manasi.d.navare, rodrigo.vivi,
alexander.deucher
[-- Attachment #1.1: Type: text/plain, Size: 1281 bytes --]
On Fri, May 04, 2018 at 03:17:59PM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
>
> As more differentation occurs between DP spec. Its useful to have these
> as macros in a drm_dp_helper.
>
> v2: DPCD_REV_XX to DP_DPCD_REV_XX
>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Tested-by: Benson Leung <bleung@chromium.org>
> ---
> include/drm/drm_dp_helper.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 91c9bcd4196f..96dcef479ed6 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -64,6 +64,11 @@
> /* AUX CH addresses */
> /* DPCD */
> #define DP_DPCD_REV 0x000
> +# define DP_DPCD_REV_10 0x10
> +# define DP_DPCD_REV_11 0x11
> +# define DP_DPCD_REV_12 0x12
> +# define DP_DPCD_REV_13 0x13
> +# define DP_DPCD_REV_14 0x14
>
> #define DP_MAX_LINK_RATE 0x001
>
> --
> 2.17.0
>
--
Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
bleung@google.com
Chromium OS Project
bleung@chromium.org
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] drm/dp: Move DPCD_REV_XX to drm_dp_helper
@ 2018-03-27 21:56 matthew.s.atwood
2018-03-27 21:56 ` [PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4 matthew.s.atwood
0 siblings, 1 reply; 9+ messages in thread
From: matthew.s.atwood @ 2018-03-27 21:56 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: alexander.deucher, Matt Atwood
From: Matt Atwood <matthew.s.atwood@intel.com>
As more differentation occurs between DP spec. Its useful to have these
as macros in a drm_dp_helper.
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/amd/display/include/dpcd_defs.h | 8 --------
include/drm/drm_dp_helper.h | 5 +++++
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
index d8e52e3..d13e0f4 100644
--- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h
+++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
@@ -28,14 +28,6 @@
#include <drm/drm_dp_helper.h>
-enum dpcd_revision {
- DPCD_REV_10 = 0x10,
- DPCD_REV_11 = 0x11,
- DPCD_REV_12 = 0x12,
- DPCD_REV_13 = 0x13,
- DPCD_REV_14 = 0x14
-};
-
/* these are the types stored at DOWNSTREAMPORT_PRESENT */
enum dpcd_downstream_port_type {
DOWNSTREAM_DP = 0,
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 4de97e9..f77746e 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -64,6 +64,11 @@
/* AUX CH addresses */
/* DPCD */
#define DP_DPCD_REV 0x000
+# define DPCD_REV_10 0x10
+# define DPCD_REV_11 0x11
+# define DPCD_REV_12 0x12
+# define DPCD_REV_13 0x13
+# define DPCD_REV_14 0x14
#define DP_MAX_LINK_RATE 0x001
--
2.7.4
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4
2018-03-27 21:56 [PATCH 1/2] drm/dp: Move DPCD_REV_XX " matthew.s.atwood
@ 2018-03-27 21:56 ` matthew.s.atwood
0 siblings, 0 replies; 9+ messages in thread
From: matthew.s.atwood @ 2018-03-27 21:56 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: alexander.deucher, harry.wentland
From: Matt Atwood <matthew.s.atwood@intel.com>
DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8
bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended
receiver capabilities. For panels that use this new feature wait interval
would be increased by 512 ms, when spec is max 16 ms. This behavior is
described in table 2-158 of DP 1.4 spec address 0000eh.
With the introduction of DP 1.4 spec main link clock recovery was
standardized to 100 us regardless of TRAINING_AUX_RD_INTERVAL value.
To avoid breaking panels that are not spec compiant we now warn on
invalid values.
V2: commit title/message, masking all 7 bits, warn on out of spec values.
V3: commit message, make link train clock recovery follow DP 1.4 spec.
V4: style changes
V5: typo
V6: print statement revisions, DP_REV to DPCD_REV, comment correction
V7: typo
V8: Style
V9: Strip out DPCD_REV_XX into seperate patch
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 22 ++++++++++++++++++----
include/drm/drm_dp_helper.h | 1 +
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index ffe14ec..f9a8bf9 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -119,18 +119,32 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
- if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
+ int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+ DP_TRAINING_AUX_RD_MASK;
+
+ if (rd_interval > 4)
+ DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",
+ rd_interval);
+
+ if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DPCD_REV_14)
udelay(100);
else
- mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+ mdelay(rd_interval * 4);
}
EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
- if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
+ int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+ DP_TRAINING_AUX_RD_MASK;
+
+ if (rd_interval > 4)
+ DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",
+ rd_interval);
+
+ if (rd_interval == 0)
udelay(400);
else
- mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+ mdelay(rd_interval * 4);
}
EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index f77746e..c1ba415 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -124,6 +124,7 @@
# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
+# define DP_TRAINING_AUX_RD_MASK 0x7F /* XXX 1.2? */
#define DP_ADAPTER_CAP 0x00f /* 1.2 */
# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
--
2.7.4
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^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-05-22 22:59 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-05-04 22:17 [PATCH 1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper matthew.s.atwood
2018-05-04 22:18 ` [PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4 matthew.s.atwood
2018-05-08 19:27 ` Rodrigo Vivi
2018-05-04 22:36 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper Patchwork
2018-05-04 22:56 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-04 23:43 ` ✓ Fi.CI.IGT: " Patchwork
2018-05-08 7:01 ` [PATCH 1/2] " Rodrigo Vivi
2018-05-22 22:59 ` Benson Leung
-- strict thread matches above, loose matches on Subject: below --
2018-03-27 21:56 [PATCH 1/2] drm/dp: Move DPCD_REV_XX " matthew.s.atwood
2018-03-27 21:56 ` [PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4 matthew.s.atwood
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