From: Aaron Lindsay <alindsay@codeaurora.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Wei Huang <wei@redhat.com>,
Michael Spradling <mspradli@codeaurora.org>,
Digant Desai <digantd@codeaurora.org>,
Peter Crosthwaite <crosthwaite.peter@gmail.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Alistair Francis <alistair.francis@xilinx.com>,
qemu-arm <qemu-arm@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v3 15/22] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions
Date: Fri, 1 Jun 2018 11:34:23 -0400 [thread overview]
Message-ID: <20180601153423.GB12424@codeaurora.org> (raw)
In-Reply-To: <CAFEAcA_2z-2utCiPQM0DtZGXgiE2qbVsB=Nn81j9DP7Z8keRqw@mail.gmail.com>
On Jun 01 09:57, Peter Maydell wrote:
> On 31 May 2018 at 21:39, Aaron Lindsay <alindsay@codeaurora.org> wrote:
> > On May 31 15:18, Peter Maydell wrote:
> >> if (arm_feature(env, ARM_FEATURE_V7VE) {
> >> /* v7 Virtualization Extensions. In real hardware this implies
> >> * EL2 and also the presence of the Security Extensions.
> >> * For QEMU, for backwards-compatibility we implement some
> >> * CPUs or CPU configs which have no actual EL2 or EL3 but do
> >> * include the various other features that V7VE implies.
> >> * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
> >> * Security Extensions is ARM_FEATURE_EL3.
> >> */
> >> set_feature(env, ARM_FEATURE_ARM_DIV);
> >
> > Is it safe to assume from your comment above regarding keeping ARM_DIV
> > separate from V7VE that the inclusion of it here is an oversight and
> > that only LPAE and V7 should be set if V7VE is? (and that V8 should
> > now directly imply both V7VE and ARM_DIV?)
>
> No; V7VE always implies ARM_DIV. (ARM_DIV doesn't imply V7VE,
> though, which is why it is a separate feature bit.)
Okay, then I'm confused about some of the preexisting logic in
kvm_arm_get_host_cpu_features. The preexisting code in that function
sets ARM_DIV and THUMB_DIV based on the appropriate bits in ID_ISAR0. If
we already knew that
> (by definition a host CPU which supports KVM has v7VE.)
and that all V7VE CPUs have ARM_DIV, why did the code there bother
checking ID_ISAR0 to begin with?
> switch (extract32(id_isar0, 24, 4)) {
> case 1:
> set_feature(&features, ARM_FEATURE_THUMB_DIV);
> break;
> case 2:
> set_feature(&features, ARM_FEATURE_ARM_DIV);
> set_feature(&features, ARM_FEATURE_THUMB_DIV);
> break;
> default:
> break;
> }
Should this switch/case be removed entirely?
-Aaron
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
next prev parent reply other threads:[~2018-06-01 15:34 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-16 20:30 [Qemu-arm] [PATCH v3 00/22] More fully implement ARM PMUv3 Aaron Lindsay
2018-03-16 20:30 ` [Qemu-arm] [PATCH v3 01/22] target/arm: A53: Initialize PMCEID[01] Aaron Lindsay
2018-03-18 22:35 ` [Qemu-devel] " Philippe Mathieu-Daudé
2018-03-18 22:57 ` Philippe Mathieu-Daudé
2018-03-19 20:35 ` Aaron Lindsay
2018-03-20 1:03 ` Philippe Mathieu-Daudé
2018-03-21 15:17 ` Aaron Lindsay
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 02/22] target/arm: A15 PMCEID0 initialization style nit Aaron Lindsay
2018-04-12 16:07 ` Peter Maydell
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 03/22] target/arm: Check PMCNTEN for whether PMCCNTR is enabled Aaron Lindsay
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 04/22] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0 Aaron Lindsay
2018-04-12 16:10 ` Peter Maydell
2018-04-12 16:56 ` Aaron Lindsay
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 05/22] target/arm: Reorganize PMCCNTR read, write, sync Aaron Lindsay
2018-04-12 16:18 ` Peter Maydell
2018-04-13 13:51 ` Aaron Lindsay
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 06/22] target/arm: Mask PMU register writes based on PMCR_EL0.N Aaron Lindsay
2018-04-12 16:24 ` Peter Maydell
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 07/22] target/arm: Fetch GICv3 state directly from CPUARMState Aaron Lindsay
2018-04-12 16:28 ` Peter Maydell
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 08/22] target/arm: Support multiple EL change hooks Aaron Lindsay
2018-03-18 22:41 ` [Qemu-devel] " Philippe Mathieu-Daudé
2018-03-20 20:45 ` Aaron Lindsay
2018-03-20 21:01 ` [Qemu-devel] " Philippe Mathieu-Daudé
2018-04-12 16:36 ` [Qemu-devel] " Peter Maydell
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 09/22] target/arm: Add pre-EL " Aaron Lindsay
2018-04-12 16:49 ` Peter Maydell
2018-04-12 17:01 ` Aaron Lindsay
2018-04-12 17:21 ` Peter Maydell
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 10/22] target/arm: Allow EL change hooks to do IO Aaron Lindsay
2018-04-12 16:53 ` Peter Maydell
2018-04-12 17:08 ` Aaron Lindsay
2018-04-12 17:21 ` Peter Maydell
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 11/22] target/arm: Fix bitmask for PMCCFILTR writes Aaron Lindsay
2018-04-12 16:41 ` [Qemu-devel] " Peter Maydell
2018-04-13 18:15 ` [Qemu-arm] " Aaron Lindsay
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 12/22] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Aaron Lindsay
2018-04-12 17:15 ` Peter Maydell
2018-04-12 17:36 ` Aaron Lindsay
2018-04-17 15:21 ` Aaron Lindsay
2018-04-17 15:37 ` Peter Maydell
2018-04-17 20:03 ` Aaron Lindsay
2018-03-16 20:31 ` [Qemu-devel] [PATCH v3 13/22] target/arm: Allow AArch32 access for PMCCFILTR Aaron Lindsay
2018-03-16 20:31 ` [Qemu-devel] [PATCH v3 14/22] target/arm: Make PMOVSCLR 64 bits wide Aaron Lindsay
2018-03-18 23:14 ` Philippe Mathieu-Daudé
2018-03-19 15:24 ` [Qemu-arm] " Aaron Lindsay
2018-03-19 15:31 ` Peter Maydell
2018-03-20 1:01 ` Philippe Mathieu-Daudé
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 15/22] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions Aaron Lindsay
2018-03-18 22:42 ` Philippe Mathieu-Daudé
2018-04-12 17:17 ` Peter Maydell
2018-04-17 14:23 ` Aaron Lindsay
2018-04-17 15:00 ` Peter Maydell
2018-04-24 20:35 ` Aaron Lindsay
2018-05-17 19:31 ` Aaron Lindsay
2018-05-31 14:18 ` Peter Maydell
2018-05-31 20:39 ` Aaron Lindsay
2018-06-01 8:57 ` Peter Maydell
2018-06-01 15:34 ` Aaron Lindsay [this message]
2018-06-01 15:59 ` [Qemu-devel] " Peter Maydell
2018-06-01 19:12 ` [Qemu-arm] " Aaron Lindsay
2018-03-16 20:31 ` [Qemu-devel] [PATCH v3 16/22] target/arm: Implement PMOVSSET Aaron Lindsay
2018-04-12 17:28 ` [Qemu-arm] " Peter Maydell
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 17/22] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled Aaron Lindsay
2018-04-12 17:29 ` Peter Maydell
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 18/22] target/arm: Add array for supported PMU events, generate PMCEID[01] Aaron Lindsay
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 19/22] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Aaron Lindsay
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 20/22] target/arm: PMU: Add instruction and cycle events Aaron Lindsay
2018-03-18 22:43 ` [Qemu-devel] " Philippe Mathieu-Daudé
2018-03-18 22:48 ` Philippe Mathieu-Daudé
2018-03-19 17:36 ` Aaron Lindsay
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 21/22] target/arm: PMU: Set PMCR.N to 4 Aaron Lindsay
2018-03-16 20:31 ` [Qemu-arm] [PATCH v3 22/22] target/arm: Implement PMSWINC Aaron Lindsay
2018-03-16 20:58 ` [Qemu-devel] [PATCH v3 00/22] More fully implement ARM PMUv3 no-reply
2018-03-17 0:01 ` [Qemu-arm] " Aaron Lindsay
2018-04-12 17:17 ` [Qemu-arm] [PATCH v3] RFC: target/arm: Send interrupts on PMU counter overflow Aaron Lindsay
2018-04-12 17:32 ` [Qemu-arm] [PATCH v3 00/22] More fully implement ARM PMUv3 Peter Maydell
2018-04-12 19:34 ` Aaron Lindsay
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