From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v13 2/3] arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable
Date: Wed, 6 Jun 2018 16:44:42 +0100 [thread overview]
Message-ID: <20180606154442.GF6631@arm.com> (raw)
In-Reply-To: <1528268481-19299-3-git-send-email-cpandya@codeaurora.org>
On Wed, Jun 06, 2018 at 12:31:20PM +0530, Chintan Pandya wrote:
> Add an interface to invalidate intermediate page tables
> from TLB for kernel.
>
> Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
> ---
> arch/arm64/include/asm/tlbflush.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index dfc61d7..a4a1901 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -218,6 +218,13 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm,
> dsb(ish);
> }
>
> +static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr)
> +{
> + unsigned long addr = __TLBI_VADDR(kaddr, 0);
> +
> + __tlbi(vaae1is, addr);
> + dsb(ish);
> +}
> #endif
Acked-by: Will Deacon <will.deacon@arm.com>
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Chintan Pandya <cpandya@codeaurora.org>
Cc: catalin.marinas@arm.com, mark.rutland@arm.com,
akpm@linux-foundation.org, toshi.kani@hpe.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v13 2/3] arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable
Date: Wed, 6 Jun 2018 16:44:42 +0100 [thread overview]
Message-ID: <20180606154442.GF6631@arm.com> (raw)
In-Reply-To: <1528268481-19299-3-git-send-email-cpandya@codeaurora.org>
On Wed, Jun 06, 2018 at 12:31:20PM +0530, Chintan Pandya wrote:
> Add an interface to invalidate intermediate page tables
> from TLB for kernel.
>
> Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
> ---
> arch/arm64/include/asm/tlbflush.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index dfc61d7..a4a1901 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -218,6 +218,13 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm,
> dsb(ish);
> }
>
> +static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr)
> +{
> + unsigned long addr = __TLBI_VADDR(kaddr, 0);
> +
> + __tlbi(vaae1is, addr);
> + dsb(ish);
> +}
> #endif
Acked-by: Will Deacon <will.deacon@arm.com>
Will
next prev parent reply other threads:[~2018-06-06 15:44 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-06 7:01 [PATCH v13 0/3] Fix issues with huge mapping in ioremap for ARM64 Chintan Pandya
2018-06-06 7:01 ` Chintan Pandya
2018-06-06 7:01 ` [PATCH v13 1/3] ioremap: Update pgtable free interfaces with addr Chintan Pandya
2018-06-06 7:01 ` Chintan Pandya
2018-06-06 15:44 ` Will Deacon
2018-06-06 15:44 ` Will Deacon
2018-06-06 7:01 ` [PATCH v13 2/3] arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable Chintan Pandya
2018-06-06 7:01 ` Chintan Pandya
2018-06-06 15:44 ` Will Deacon [this message]
2018-06-06 15:44 ` Will Deacon
2018-06-06 7:01 ` [PATCH v13 3/3] arm64: Implement page table free interfaces Chintan Pandya
2018-06-06 7:01 ` Chintan Pandya
2018-06-06 15:44 ` Will Deacon
2018-06-06 15:44 ` Will Deacon
2018-09-20 17:25 ` Catalin Marinas
2018-09-20 17:25 ` Catalin Marinas
2018-09-21 9:56 ` Catalin Marinas
2018-09-21 9:56 ` Catalin Marinas
2018-06-06 15:45 ` [PATCH v13 0/3] Fix issues with huge mapping in ioremap for ARM64 Will Deacon
2018-06-06 15:45 ` Will Deacon
2018-06-07 8:03 ` Chintan Pandya
2018-06-07 8:03 ` Chintan Pandya
2018-06-12 6:47 ` Chintan Pandya
2018-06-12 6:47 ` Chintan Pandya
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