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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: stable@vger.kernel.org
Subject: Re: [PATCH 2/4] drm/i915: Fix hotplug irq ack on i965/g4x
Date: Thu, 14 Jun 2018 19:27:57 +0300	[thread overview]
Message-ID: <20180614162757.GJ20518@intel.com> (raw)
In-Reply-To: <20180611200258.27121-2-ville.syrjala@linux.intel.com>

On Mon, Jun 11, 2018 at 11:02:56PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Just like with PIPESTAT, the edge triggered IIR on i965/g4x
> also causes problems for hotplug interrupts. To make sure
> we don't get the IIR port interrupt bit stuck low with the
> ISR bit high we must force an edge in ISR. We do that by
> clearing PORT_HOTPLUG_EN temporaryly when we ack
> PORT_HOTPLUG_STAT.
> 
> Cc: stable@vger.kernel.org
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 31 ++++++++++++++++++++++++++++---
>  1 file changed, 28 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 364e1c85315e..59250ecbd0d9 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1998,10 +1998,35 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
>  
>  static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
>  {
> -	u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
> +	u32 hotplug_status, hotplug_en;
>  
> -	if (hotplug_status)
> -		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
> +	hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
> +
> +	if (IS_G4X(dev_priv) ||
> +	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> +		hotplug_status &= HOTPLUG_INT_STATUS_G4X |
> +			DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
> +	else
> +		hotplug_status &= HOTPLUG_INT_STATUS_I915;
> +
> +	if (hotplug_status == 0)
> +		return 0;
> +
> +	spin_lock(&dev_priv->irq_lock);
> +
> +	/*
> +	 * Toggle all PORT_HOTPLUG_EN bits to make sure we
> +	 * get an edge in the ISR port interrupt bit if we
> +	 * don't clear all the enabled status bits. Otherwise
> +	 * the edge triggered IIR on i965/g4x wouldn't notice
> +	 * that an interrupt is still pending.
> +	 */
> +	hotplug_en = I915_READ(PORT_HOTPLUG_EN);
> +	I915_WRITE(PORT_HOTPLUG_EN, 0);
> +	I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
> +	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);

Actually this seems to be a bad idea. At least one elk here likes
to signal a long pulse on disconnected ports every time I toggle
the enable bit in PORT_HOTPLUG_EN. The spec even warns that something
like this could happen. Not sure why it specifically happens for
ports where nothing is connected. Feels like it should be the other
way around.

So looks like I'll need to come up with some other way to guarantee
the ISR edge. Can't immediately think of any way apart from clearing
PORT_HOTPLUG_STAT in a loop :(

> +
> +	spin_unlock(&dev_priv->irq_lock);
>  
>  	return hotplug_status;
>  }
> -- 
> 2.16.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix hotplug irq ack on i965/g4x
Date: Thu, 14 Jun 2018 19:27:57 +0300	[thread overview]
Message-ID: <20180614162757.GJ20518@intel.com> (raw)
In-Reply-To: <20180611200258.27121-2-ville.syrjala@linux.intel.com>

On Mon, Jun 11, 2018 at 11:02:56PM +0300, Ville Syrjala wrote:
> From: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> 
> Just like with PIPESTAT, the edge triggered IIR on i965/g4x
> also causes problems for hotplug interrupts. To make sure
> we don't get the IIR port interrupt bit stuck low with the
> ISR bit high we must force an edge in ISR. We do that by
> clearing PORT_HOTPLUG_EN temporaryly when we ack
> PORT_HOTPLUG_STAT.
> 
> Cc: stable@vger.kernel.org
> Signed-off-by: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 31 ++++++++++++++++++++++++++++---
>  1 file changed, 28 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 364e1c85315e..59250ecbd0d9 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1998,10 +1998,35 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
>  
>  static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
>  {
> -	u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
> +	u32 hotplug_status, hotplug_en;
>  
> -	if (hotplug_status)
> -		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
> +	hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
> +
> +	if (IS_G4X(dev_priv) ||
> +	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> +		hotplug_status &= HOTPLUG_INT_STATUS_G4X |
> +			DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
> +	else
> +		hotplug_status &= HOTPLUG_INT_STATUS_I915;
> +
> +	if (hotplug_status == 0)
> +		return 0;
> +
> +	spin_lock(&dev_priv->irq_lock);
> +
> +	/*
> +	 * Toggle all PORT_HOTPLUG_EN bits to make sure we
> +	 * get an edge in the ISR port interrupt bit if we
> +	 * don't clear all the enabled status bits. Otherwise
> +	 * the edge triggered IIR on i965/g4x wouldn't notice
> +	 * that an interrupt is still pending.
> +	 */
> +	hotplug_en = I915_READ(PORT_HOTPLUG_EN);
> +	I915_WRITE(PORT_HOTPLUG_EN, 0);
> +	I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
> +	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);

Actually this seems to be a bad idea. At least one elk here likes
to signal a long pulse on disconnected ports every time I toggle
the enable bit in PORT_HOTPLUG_EN. The spec even warns that something
like this could happen. Not sure why it specifically happens for
ports where nothing is connected. Feels like it should be the other
way around.

So looks like I'll need to come up with some other way to guarantee
the ISR edge. Can't immediately think of any way apart from clearing
PORT_HOTPLUG_STAT in a loop :(

> +
> +	spin_unlock(&dev_priv->irq_lock);
>  
>  	return hotplug_status;
>  }
> -- 
> 2.16.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrj�l�
Intel

  parent reply	other threads:[~2018-06-14 16:28 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-11 20:02 [PATCH 1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x Ville Syrjala
2018-06-11 20:02 ` [PATCH 2/4] drm/i915: Fix hotplug " Ville Syrjala
2018-06-11 20:58   ` [Intel-gfx] " Chris Wilson
2018-06-14 16:27   ` Ville Syrjälä [this message]
2018-06-14 16:27     ` Ville Syrjälä
2018-06-14 17:56   ` [PATCH v2 " Ville Syrjala
2018-07-03  9:56     ` [Intel-gfx] " Imre Deak
2018-07-03  9:56       ` Imre Deak
2018-06-11 20:02 ` [PATCH 3/4] drm/i915: Fix pre-ILK error interrupt ack Ville Syrjala
2018-07-03 11:58   ` [Intel-gfx] " Imre Deak
2018-07-03 11:58     ` Imre Deak
2018-06-11 20:02 ` [PATCH 4/4] drm/i915: Unmask and enable master error interrupt on gen2/3 Ville Syrjala
2018-07-03 12:00   ` Imre Deak
2018-06-11 20:46 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x Patchwork
2018-06-11 20:53 ` [Intel-gfx] [PATCH 1/4] " Chris Wilson
2018-06-14 18:16   ` Ville Syrjälä
2018-06-14 18:16     ` Ville Syrjälä
2018-06-12  2:34 ` ✓ Fi.CI.IGT: success for series starting with [1/4] " Patchwork
2018-06-14 18:20 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x (rev2) Patchwork
2018-06-15  2:11 ` ✓ Fi.CI.IGT: " Patchwork

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