[MODERATED] Re: [PATCH v2.1 3/6] [PATCH v2.1 3/6] Patch #3

[Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>]

On Thu, Jun 21, 2018 at 09:58:32AM +0200, speck for Thomas Gleixner wrote:
> On Wed, 20 Jun 2018, speck for Konrad Rzeszutek Wilk wrote:
> > > diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
> > > index 50500cea6eba..659963bf9a3c 100644
> > > --- a/arch/x86/kernel/cpu/bugs.c
> > > +++ b/arch/x86/kernel/cpu/bugs.c
> > > @@ -53,6 +53,13 @@ static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
> > >  u64 __ro_after_init x86_amd_ls_cfg_base;
> > >  u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
> > >  
> > > +/*
> > > + * Our boot-time value of the IA32_FLUSH_CMD MSR. We read it once so that
> > > + * any writes to the IA32_FLUSH_CMD contain whatever reserved bits have been
> > > + * set.
> > > + */
> > > +static u64 __ro_after_init x86_flush_cmd;
> > > +
> > >  void __init check_bugs(void)
> > >  {
> > >  	identify_boot_cpu();
> > > @@ -85,6 +92,10 @@ void __init check_bugs(void)
> > >  
> > >  	l1tf_select_mitigation();
> > >  
> > > +	/* Similar to SPEC_CTRL MSR, read it to account for reserved bits. */
> > > +	if (boot_cpu_has(X86_FEATURE_FLUSH_L1D))
> > > +		rdmsrl(MSR_IA32_FLUSH_CMD, x86_flush_cmd);
> > 
> > 
> > The spec didn't mention it but the development microcode I am assuming looks to be a
> > write-only MSR, so I changed this to:
> > 
> > 		(void)rdmsrl_safe(MSR_IA32_FLUSH_CMD, &x86_flush_cmd);
> 
> Which is pointless as my version of that magic PDF clearly says:
> 
>   New MSR IA32_FLUSH_CMD (MSR 0x10B, Write-only) bit 0: L1D Flush

Duh. Indeed. <rips it out>
> 
> Thanks,
> 
> 	tglx