* [PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events @ 2018-07-31 10:02 ` Ganapatrao Kulkarni 0 siblings, 0 replies; 11+ messages in thread From: Ganapatrao Kulkarni @ 2018-07-31 10:02 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> --- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 87 +++++++++++++++++++++- 1 file changed, 84 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json index bc03c06..752e47e 100644 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json @@ -12,6 +12,21 @@ "ArchStdEvent": "L1D_CACHE_REFILL_WR", }, { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL", + }, + { "ArchStdEvent": "L1D_TLB_REFILL_RD", }, { @@ -24,9 +39,75 @@ "ArchStdEvent": "L1D_TLB_WR", }, { + "ArchStdEvent": "L2D_TLB_REFILL_RD", + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_WR", + }, + { + "ArchStdEvent": "L2D_TLB_RD", + }, + { + "ArchStdEvent": "L2D_TLB_WR", + }, + { "ArchStdEvent": "BUS_ACCESS_RD", - }, - { + }, + { "ArchStdEvent": "BUS_ACCESS_WR", - } + }, + { + "ArchStdEvent": "MEM_ACCESS_RD", + }, + { + "ArchStdEvent": "MEM_ACCESS_WR", + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC", + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC", + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC", + }, + { + "ArchStdEvent": "EXC_UNDEF", + }, + { + "ArchStdEvent": "EXC_SVC", + }, + { + "ArchStdEvent": "EXC_PABORT", + }, + { + "ArchStdEvent": "EXC_DABORT", + }, + { + "ArchStdEvent": "EXC_IRQ", + }, + { + "ArchStdEvent": "EXC_FIQ", + }, + { + "ArchStdEvent": "EXC_SMC", + }, + { + "ArchStdEvent": "EXC_HVC", + }, + { + "ArchStdEvent": "EXC_TRAP_PABORT", + }, + { + "ArchStdEvent": "EXC_TRAP_DABORT", + }, + { + "ArchStdEvent": "EXC_TRAP_OTHER", + }, + { + "ArchStdEvent": "EXC_TRAP_IRQ", + }, + { + "ArchStdEvent": "EXC_TRAP_FIQ", + } ] -- 2.9.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events @ 2018-07-31 10:02 ` Ganapatrao Kulkarni 0 siblings, 0 replies; 11+ messages in thread From: Ganapatrao Kulkarni @ 2018-07-31 10:02 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel Cc: acme, alexander.shishkin, jolsa, namhyung, peterz, mingo, Will.Deacon, mark.rutland, jnair, Robert.Richter, Vadim.Lomovtsev, Jan.Glauber, gklkml16 Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> --- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 87 +++++++++++++++++++++- 1 file changed, 84 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json index bc03c06..752e47e 100644 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json @@ -12,6 +12,21 @@ "ArchStdEvent": "L1D_CACHE_REFILL_WR", }, { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL", + }, + { "ArchStdEvent": "L1D_TLB_REFILL_RD", }, { @@ -24,9 +39,75 @@ "ArchStdEvent": "L1D_TLB_WR", }, { + "ArchStdEvent": "L2D_TLB_REFILL_RD", + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_WR", + }, + { + "ArchStdEvent": "L2D_TLB_RD", + }, + { + "ArchStdEvent": "L2D_TLB_WR", + }, + { "ArchStdEvent": "BUS_ACCESS_RD", - }, - { + }, + { "ArchStdEvent": "BUS_ACCESS_WR", - } + }, + { + "ArchStdEvent": "MEM_ACCESS_RD", + }, + { + "ArchStdEvent": "MEM_ACCESS_WR", + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC", + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC", + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC", + }, + { + "ArchStdEvent": "EXC_UNDEF", + }, + { + "ArchStdEvent": "EXC_SVC", + }, + { + "ArchStdEvent": "EXC_PABORT", + }, + { + "ArchStdEvent": "EXC_DABORT", + }, + { + "ArchStdEvent": "EXC_IRQ", + }, + { + "ArchStdEvent": "EXC_FIQ", + }, + { + "ArchStdEvent": "EXC_SMC", + }, + { + "ArchStdEvent": "EXC_HVC", + }, + { + "ArchStdEvent": "EXC_TRAP_PABORT", + }, + { + "ArchStdEvent": "EXC_TRAP_DABORT", + }, + { + "ArchStdEvent": "EXC_TRAP_OTHER", + }, + { + "ArchStdEvent": "EXC_TRAP_IRQ", + }, + { + "ArchStdEvent": "EXC_TRAP_FIQ", + } ] -- 2.9.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events 2018-07-31 10:02 ` Ganapatrao Kulkarni @ 2018-07-31 14:28 ` Arnaldo Carvalho de Melo -1 siblings, 0 replies; 11+ messages in thread From: Arnaldo Carvalho de Melo @ 2018-07-31 14:28 UTC (permalink / raw) To: linux-arm-kernel Em Tue, Jul 31, 2018 at 03:32:51PM +0530, Ganapatrao Kulkarni escreveu: > Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Can you please consider to provide an example of such counters being used, i.e. with a simple C synthetic test that causes these events to take place, then run it via 'perf stat' to show that indeed, they are being programmed and read correctly? Ideally for all of them, but if that becomes too burdensome, for a few of them? Thanks, - Arnaldo > --- > .../arch/arm64/cavium/thunderx2/core-imp-def.json | 87 +++++++++++++++++++++- > 1 file changed, 84 insertions(+), 3 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json > index bc03c06..752e47e 100644 > --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json > +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json > @@ -12,6 +12,21 @@ > "ArchStdEvent": "L1D_CACHE_REFILL_WR", > }, > { > + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", > + }, > + { > + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", > + }, > + { > + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", > + }, > + { > + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", > + }, > + { > + "ArchStdEvent": "L1D_CACHE_INVAL", > + }, > + { > "ArchStdEvent": "L1D_TLB_REFILL_RD", > }, > { > @@ -24,9 +39,75 @@ > "ArchStdEvent": "L1D_TLB_WR", > }, > { > + "ArchStdEvent": "L2D_TLB_REFILL_RD", > + }, > + { > + "ArchStdEvent": "L2D_TLB_REFILL_WR", > + }, > + { > + "ArchStdEvent": "L2D_TLB_RD", > + }, > + { > + "ArchStdEvent": "L2D_TLB_WR", > + }, > + { > "ArchStdEvent": "BUS_ACCESS_RD", > - }, > - { > + }, > + { > "ArchStdEvent": "BUS_ACCESS_WR", > - } > + }, > + { > + "ArchStdEvent": "MEM_ACCESS_RD", > + }, > + { > + "ArchStdEvent": "MEM_ACCESS_WR", > + }, > + { > + "ArchStdEvent": "UNALIGNED_LD_SPEC", > + }, > + { > + "ArchStdEvent": "UNALIGNED_ST_SPEC", > + }, > + { > + "ArchStdEvent": "UNALIGNED_LDST_SPEC", > + }, > + { > + "ArchStdEvent": "EXC_UNDEF", > + }, > + { > + "ArchStdEvent": "EXC_SVC", > + }, > + { > + "ArchStdEvent": "EXC_PABORT", > + }, > + { > + "ArchStdEvent": "EXC_DABORT", > + }, > + { > + "ArchStdEvent": "EXC_IRQ", > + }, > + { > + "ArchStdEvent": "EXC_FIQ", > + }, > + { > + "ArchStdEvent": "EXC_SMC", > + }, > + { > + "ArchStdEvent": "EXC_HVC", > + }, > + { > + "ArchStdEvent": "EXC_TRAP_PABORT", > + }, > + { > + "ArchStdEvent": "EXC_TRAP_DABORT", > + }, > + { > + "ArchStdEvent": "EXC_TRAP_OTHER", > + }, > + { > + "ArchStdEvent": "EXC_TRAP_IRQ", > + }, > + { > + "ArchStdEvent": "EXC_TRAP_FIQ", > + } > ] > -- > 2.9.4 ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events @ 2018-07-31 14:28 ` Arnaldo Carvalho de Melo 0 siblings, 0 replies; 11+ messages in thread From: Arnaldo Carvalho de Melo @ 2018-07-31 14:28 UTC (permalink / raw) To: Ganapatrao Kulkarni Cc: linux-kernel, linux-arm-kernel, alexander.shishkin, jolsa, namhyung, peterz, mingo, Will.Deacon, mark.rutland, jnair, Robert.Richter, Vadim.Lomovtsev, Jan.Glauber, gklkml16 Em Tue, Jul 31, 2018 at 03:32:51PM +0530, Ganapatrao Kulkarni escreveu: > Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Can you please consider to provide an example of such counters being used, i.e. with a simple C synthetic test that causes these events to take place, then run it via 'perf stat' to show that indeed, they are being programmed and read correctly? Ideally for all of them, but if that becomes too burdensome, for a few of them? Thanks, - Arnaldo > --- > .../arch/arm64/cavium/thunderx2/core-imp-def.json | 87 +++++++++++++++++++++- > 1 file changed, 84 insertions(+), 3 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json > index bc03c06..752e47e 100644 > --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json > +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json > @@ -12,6 +12,21 @@ > "ArchStdEvent": "L1D_CACHE_REFILL_WR", > }, > { > + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", > + }, > + { > + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", > + }, > + { > + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", > + }, > + { > + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", > + }, > + { > + "ArchStdEvent": "L1D_CACHE_INVAL", > + }, > + { > "ArchStdEvent": "L1D_TLB_REFILL_RD", > }, > { > @@ -24,9 +39,75 @@ > "ArchStdEvent": "L1D_TLB_WR", > }, > { > + "ArchStdEvent": "L2D_TLB_REFILL_RD", > + }, > + { > + "ArchStdEvent": "L2D_TLB_REFILL_WR", > + }, > + { > + "ArchStdEvent": "L2D_TLB_RD", > + }, > + { > + "ArchStdEvent": "L2D_TLB_WR", > + }, > + { > "ArchStdEvent": "BUS_ACCESS_RD", > - }, > - { > + }, > + { > "ArchStdEvent": "BUS_ACCESS_WR", > - } > + }, > + { > + "ArchStdEvent": "MEM_ACCESS_RD", > + }, > + { > + "ArchStdEvent": "MEM_ACCESS_WR", > + }, > + { > + "ArchStdEvent": "UNALIGNED_LD_SPEC", > + }, > + { > + "ArchStdEvent": "UNALIGNED_ST_SPEC", > + }, > + { > + "ArchStdEvent": "UNALIGNED_LDST_SPEC", > + }, > + { > + "ArchStdEvent": "EXC_UNDEF", > + }, > + { > + "ArchStdEvent": "EXC_SVC", > + }, > + { > + "ArchStdEvent": "EXC_PABORT", > + }, > + { > + "ArchStdEvent": "EXC_DABORT", > + }, > + { > + "ArchStdEvent": "EXC_IRQ", > + }, > + { > + "ArchStdEvent": "EXC_FIQ", > + }, > + { > + "ArchStdEvent": "EXC_SMC", > + }, > + { > + "ArchStdEvent": "EXC_HVC", > + }, > + { > + "ArchStdEvent": "EXC_TRAP_PABORT", > + }, > + { > + "ArchStdEvent": "EXC_TRAP_DABORT", > + }, > + { > + "ArchStdEvent": "EXC_TRAP_OTHER", > + }, > + { > + "ArchStdEvent": "EXC_TRAP_IRQ", > + }, > + { > + "ArchStdEvent": "EXC_TRAP_FIQ", > + } > ] > -- > 2.9.4 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events 2018-07-31 14:28 ` Arnaldo Carvalho de Melo @ 2018-07-31 15:10 ` Ganapatrao Kulkarni -1 siblings, 0 replies; 11+ messages in thread From: Ganapatrao Kulkarni @ 2018-07-31 15:10 UTC (permalink / raw) To: linux-arm-kernel Hi Arnaldo, On Tue, Jul 31, 2018 at 7:58 PM, Arnaldo Carvalho de Melo <arnaldo.melo@gmail.com> wrote: > Em Tue, Jul 31, 2018 at 03:32:51PM +0530, Ganapatrao Kulkarni escreveu: >> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> > > Can you please consider to provide an example of such counters being > used, i.e. with a simple C synthetic test that causes these events to > take place, then run it via 'perf stat' to show that indeed, they are > being programmed and read correctly? > > Ideally for all of them, but if that becomes too burdensome, for a few > of them? It may be tedious for all, certainly I will provide the test results/log for some of them(as many as possible). > > Thanks, > > - Arnaldo > >> --- >> .../arch/arm64/cavium/thunderx2/core-imp-def.json | 87 +++++++++++++++++++++- >> 1 file changed, 84 insertions(+), 3 deletions(-) >> >> diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json >> index bc03c06..752e47e 100644 >> --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json >> +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json >> @@ -12,6 +12,21 @@ >> "ArchStdEvent": "L1D_CACHE_REFILL_WR", >> }, >> { >> + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", >> + }, >> + { >> + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", >> + }, >> + { >> + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", >> + }, >> + { >> + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", >> + }, >> + { >> + "ArchStdEvent": "L1D_CACHE_INVAL", >> + }, >> + { >> "ArchStdEvent": "L1D_TLB_REFILL_RD", >> }, >> { >> @@ -24,9 +39,75 @@ >> "ArchStdEvent": "L1D_TLB_WR", >> }, >> { >> + "ArchStdEvent": "L2D_TLB_REFILL_RD", >> + }, >> + { >> + "ArchStdEvent": "L2D_TLB_REFILL_WR", >> + }, >> + { >> + "ArchStdEvent": "L2D_TLB_RD", >> + }, >> + { >> + "ArchStdEvent": "L2D_TLB_WR", >> + }, >> + { >> "ArchStdEvent": "BUS_ACCESS_RD", >> - }, >> - { >> + }, >> + { >> "ArchStdEvent": "BUS_ACCESS_WR", >> - } >> + }, >> + { >> + "ArchStdEvent": "MEM_ACCESS_RD", >> + }, >> + { >> + "ArchStdEvent": "MEM_ACCESS_WR", >> + }, >> + { >> + "ArchStdEvent": "UNALIGNED_LD_SPEC", >> + }, >> + { >> + "ArchStdEvent": "UNALIGNED_ST_SPEC", >> + }, >> + { >> + "ArchStdEvent": "UNALIGNED_LDST_SPEC", >> + }, >> + { >> + "ArchStdEvent": "EXC_UNDEF", >> + }, >> + { >> + "ArchStdEvent": "EXC_SVC", >> + }, >> + { >> + "ArchStdEvent": "EXC_PABORT", >> + }, >> + { >> + "ArchStdEvent": "EXC_DABORT", >> + }, >> + { >> + "ArchStdEvent": "EXC_IRQ", >> + }, >> + { >> + "ArchStdEvent": "EXC_FIQ", >> + }, >> + { >> + "ArchStdEvent": "EXC_SMC", >> + }, >> + { >> + "ArchStdEvent": "EXC_HVC", >> + }, >> + { >> + "ArchStdEvent": "EXC_TRAP_PABORT", >> + }, >> + { >> + "ArchStdEvent": "EXC_TRAP_DABORT", >> + }, >> + { >> + "ArchStdEvent": "EXC_TRAP_OTHER", >> + }, >> + { >> + "ArchStdEvent": "EXC_TRAP_IRQ", >> + }, >> + { >> + "ArchStdEvent": "EXC_TRAP_FIQ", >> + } >> ] >> -- >> 2.9.4 thanks Ganapat ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events @ 2018-07-31 15:10 ` Ganapatrao Kulkarni 0 siblings, 0 replies; 11+ messages in thread From: Ganapatrao Kulkarni @ 2018-07-31 15:10 UTC (permalink / raw) To: Arnaldo Carvalho de Melo Cc: Ganapatrao Kulkarni, LKML, linux-arm-kernel, Alexander Shishkin, Jiri Olsa, namhyung, Peter Zijlstra, Ingo Molnar, Will Deacon, Mark Rutland, jnair, Robert Richter, Vadim.Lomovtsev, Jan.Glauber Hi Arnaldo, On Tue, Jul 31, 2018 at 7:58 PM, Arnaldo Carvalho de Melo <arnaldo.melo@gmail.com> wrote: > Em Tue, Jul 31, 2018 at 03:32:51PM +0530, Ganapatrao Kulkarni escreveu: >> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> > > Can you please consider to provide an example of such counters being > used, i.e. with a simple C synthetic test that causes these events to > take place, then run it via 'perf stat' to show that indeed, they are > being programmed and read correctly? > > Ideally for all of them, but if that becomes too burdensome, for a few > of them? It may be tedious for all, certainly I will provide the test results/log for some of them(as many as possible). > > Thanks, > > - Arnaldo > >> --- >> .../arch/arm64/cavium/thunderx2/core-imp-def.json | 87 +++++++++++++++++++++- >> 1 file changed, 84 insertions(+), 3 deletions(-) >> >> diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json >> index bc03c06..752e47e 100644 >> --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json >> +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json >> @@ -12,6 +12,21 @@ >> "ArchStdEvent": "L1D_CACHE_REFILL_WR", >> }, >> { >> + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", >> + }, >> + { >> + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", >> + }, >> + { >> + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", >> + }, >> + { >> + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", >> + }, >> + { >> + "ArchStdEvent": "L1D_CACHE_INVAL", >> + }, >> + { >> "ArchStdEvent": "L1D_TLB_REFILL_RD", >> }, >> { >> @@ -24,9 +39,75 @@ >> "ArchStdEvent": "L1D_TLB_WR", >> }, >> { >> + "ArchStdEvent": "L2D_TLB_REFILL_RD", >> + }, >> + { >> + "ArchStdEvent": "L2D_TLB_REFILL_WR", >> + }, >> + { >> + "ArchStdEvent": "L2D_TLB_RD", >> + }, >> + { >> + "ArchStdEvent": "L2D_TLB_WR", >> + }, >> + { >> "ArchStdEvent": "BUS_ACCESS_RD", >> - }, >> - { >> + }, >> + { >> "ArchStdEvent": "BUS_ACCESS_WR", >> - } >> + }, >> + { >> + "ArchStdEvent": "MEM_ACCESS_RD", >> + }, >> + { >> + "ArchStdEvent": "MEM_ACCESS_WR", >> + }, >> + { >> + "ArchStdEvent": "UNALIGNED_LD_SPEC", >> + }, >> + { >> + "ArchStdEvent": "UNALIGNED_ST_SPEC", >> + }, >> + { >> + "ArchStdEvent": "UNALIGNED_LDST_SPEC", >> + }, >> + { >> + "ArchStdEvent": "EXC_UNDEF", >> + }, >> + { >> + "ArchStdEvent": "EXC_SVC", >> + }, >> + { >> + "ArchStdEvent": "EXC_PABORT", >> + }, >> + { >> + "ArchStdEvent": "EXC_DABORT", >> + }, >> + { >> + "ArchStdEvent": "EXC_IRQ", >> + }, >> + { >> + "ArchStdEvent": "EXC_FIQ", >> + }, >> + { >> + "ArchStdEvent": "EXC_SMC", >> + }, >> + { >> + "ArchStdEvent": "EXC_HVC", >> + }, >> + { >> + "ArchStdEvent": "EXC_TRAP_PABORT", >> + }, >> + { >> + "ArchStdEvent": "EXC_TRAP_DABORT", >> + }, >> + { >> + "ArchStdEvent": "EXC_TRAP_OTHER", >> + }, >> + { >> + "ArchStdEvent": "EXC_TRAP_IRQ", >> + }, >> + { >> + "ArchStdEvent": "EXC_TRAP_FIQ", >> + } >> ] >> -- >> 2.9.4 thanks Ganapat ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events 2018-07-31 15:10 ` Ganapatrao Kulkarni @ 2018-07-31 17:29 ` Arnaldo Carvalho de Melo -1 siblings, 0 replies; 11+ messages in thread From: Arnaldo Carvalho de Melo @ 2018-07-31 17:29 UTC (permalink / raw) To: linux-arm-kernel Em Tue, Jul 31, 2018 at 08:40:51PM +0530, Ganapatrao Kulkarni escreveu: > Hi Arnaldo, > > On Tue, Jul 31, 2018 at 7:58 PM, Arnaldo Carvalho de Melo > <arnaldo.melo@gmail.com> wrote: > > Em Tue, Jul 31, 2018 at 03:32:51PM +0530, Ganapatrao Kulkarni escreveu: > >> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> > > > > Can you please consider to provide an example of such counters being > > used, i.e. with a simple C synthetic test that causes these events to > > take place, then run it via 'perf stat' to show that indeed, they are > > being programmed and read correctly? > > > > Ideally for all of them, but if that becomes too burdensome, for a few > > of them? > > It may be tedious for all, certainly I will provide the test > results/log for some of them(as many as possible). Right, we do try to test some of the events via 'perf test', for instance: [root at jouet perf]# perf test openat 2: Detect openat syscall event : Ok 3: Detect openat syscall event on all cpus : Ok 15: syscalls:sys_enter_openat event fields : Ok [root at jouet perf]# Things like setting up evsels for some events, then forking + calling a syscall, then checking if that event appeared on the ring buffer, check if the payload for the event, as read using the tracefs format fields matches the parameters we passed in the syscall, etc. See tools/perf/tests/openat-syscall-tp-fields.c for that "syscalls:sys_enter_openat event fields" specific source code. So doing some of these synthetic tests when updating the event files may help us in the direction of having tests that run on those specific hardwares (ThunderX2 in this case) everytime we run 'perf test', so that we can detect failures sooner. I.e. first write a simple test for one of those events, use it as documentation, at some point, as time permits, turn those into a 'perf test' entry. Thanks, - Arnaldo > > > > Thanks, > > > > - Arnaldo > > > >> --- > >> .../arch/arm64/cavium/thunderx2/core-imp-def.json | 87 +++++++++++++++++++++- > >> 1 file changed, 84 insertions(+), 3 deletions(-) > >> > >> diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json > >> index bc03c06..752e47e 100644 > >> --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json > >> +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json > >> @@ -12,6 +12,21 @@ > >> "ArchStdEvent": "L1D_CACHE_REFILL_WR", > >> }, > >> { > >> + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", > >> + }, > >> + { > >> + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", > >> + }, > >> + { > >> + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", > >> + }, > >> + { > >> + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", > >> + }, > >> + { > >> + "ArchStdEvent": "L1D_CACHE_INVAL", > >> + }, > >> + { > >> "ArchStdEvent": "L1D_TLB_REFILL_RD", > >> }, > >> { > >> @@ -24,9 +39,75 @@ > >> "ArchStdEvent": "L1D_TLB_WR", > >> }, > >> { > >> + "ArchStdEvent": "L2D_TLB_REFILL_RD", > >> + }, > >> + { > >> + "ArchStdEvent": "L2D_TLB_REFILL_WR", > >> + }, > >> + { > >> + "ArchStdEvent": "L2D_TLB_RD", > >> + }, > >> + { > >> + "ArchStdEvent": "L2D_TLB_WR", > >> + }, > >> + { > >> "ArchStdEvent": "BUS_ACCESS_RD", > >> - }, > >> - { > >> + }, > >> + { > >> "ArchStdEvent": "BUS_ACCESS_WR", > >> - } > >> + }, > >> + { > >> + "ArchStdEvent": "MEM_ACCESS_RD", > >> + }, > >> + { > >> + "ArchStdEvent": "MEM_ACCESS_WR", > >> + }, > >> + { > >> + "ArchStdEvent": "UNALIGNED_LD_SPEC", > >> + }, > >> + { > >> + "ArchStdEvent": "UNALIGNED_ST_SPEC", > >> + }, > >> + { > >> + "ArchStdEvent": "UNALIGNED_LDST_SPEC", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_UNDEF", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_SVC", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_PABORT", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_DABORT", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_IRQ", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_FIQ", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_SMC", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_HVC", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_TRAP_PABORT", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_TRAP_DABORT", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_TRAP_OTHER", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_TRAP_IRQ", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_TRAP_FIQ", > >> + } > >> ] > >> -- > >> 2.9.4 > > thanks > Ganapat ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events @ 2018-07-31 17:29 ` Arnaldo Carvalho de Melo 0 siblings, 0 replies; 11+ messages in thread From: Arnaldo Carvalho de Melo @ 2018-07-31 17:29 UTC (permalink / raw) To: Ganapatrao Kulkarni Cc: Arnaldo Carvalho de Melo, Ganapatrao Kulkarni, LKML, linux-arm-kernel, Alexander Shishkin, Jiri Olsa, namhyung, Peter Zijlstra, Ingo Molnar, Will Deacon, Mark Rutland, jnair, Robert Richter, Vadim.Lomovtsev, Jan.Glauber Em Tue, Jul 31, 2018 at 08:40:51PM +0530, Ganapatrao Kulkarni escreveu: > Hi Arnaldo, > > On Tue, Jul 31, 2018 at 7:58 PM, Arnaldo Carvalho de Melo > <arnaldo.melo@gmail.com> wrote: > > Em Tue, Jul 31, 2018 at 03:32:51PM +0530, Ganapatrao Kulkarni escreveu: > >> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> > > > > Can you please consider to provide an example of such counters being > > used, i.e. with a simple C synthetic test that causes these events to > > take place, then run it via 'perf stat' to show that indeed, they are > > being programmed and read correctly? > > > > Ideally for all of them, but if that becomes too burdensome, for a few > > of them? > > It may be tedious for all, certainly I will provide the test > results/log for some of them(as many as possible). Right, we do try to test some of the events via 'perf test', for instance: [root@jouet perf]# perf test openat 2: Detect openat syscall event : Ok 3: Detect openat syscall event on all cpus : Ok 15: syscalls:sys_enter_openat event fields : Ok [root@jouet perf]# Things like setting up evsels for some events, then forking + calling a syscall, then checking if that event appeared on the ring buffer, check if the payload for the event, as read using the tracefs format fields matches the parameters we passed in the syscall, etc. See tools/perf/tests/openat-syscall-tp-fields.c for that "syscalls:sys_enter_openat event fields" specific source code. So doing some of these synthetic tests when updating the event files may help us in the direction of having tests that run on those specific hardwares (ThunderX2 in this case) everytime we run 'perf test', so that we can detect failures sooner. I.e. first write a simple test for one of those events, use it as documentation, at some point, as time permits, turn those into a 'perf test' entry. Thanks, - Arnaldo > > > > Thanks, > > > > - Arnaldo > > > >> --- > >> .../arch/arm64/cavium/thunderx2/core-imp-def.json | 87 +++++++++++++++++++++- > >> 1 file changed, 84 insertions(+), 3 deletions(-) > >> > >> diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json > >> index bc03c06..752e47e 100644 > >> --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json > >> +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json > >> @@ -12,6 +12,21 @@ > >> "ArchStdEvent": "L1D_CACHE_REFILL_WR", > >> }, > >> { > >> + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", > >> + }, > >> + { > >> + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", > >> + }, > >> + { > >> + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", > >> + }, > >> + { > >> + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", > >> + }, > >> + { > >> + "ArchStdEvent": "L1D_CACHE_INVAL", > >> + }, > >> + { > >> "ArchStdEvent": "L1D_TLB_REFILL_RD", > >> }, > >> { > >> @@ -24,9 +39,75 @@ > >> "ArchStdEvent": "L1D_TLB_WR", > >> }, > >> { > >> + "ArchStdEvent": "L2D_TLB_REFILL_RD", > >> + }, > >> + { > >> + "ArchStdEvent": "L2D_TLB_REFILL_WR", > >> + }, > >> + { > >> + "ArchStdEvent": "L2D_TLB_RD", > >> + }, > >> + { > >> + "ArchStdEvent": "L2D_TLB_WR", > >> + }, > >> + { > >> "ArchStdEvent": "BUS_ACCESS_RD", > >> - }, > >> - { > >> + }, > >> + { > >> "ArchStdEvent": "BUS_ACCESS_WR", > >> - } > >> + }, > >> + { > >> + "ArchStdEvent": "MEM_ACCESS_RD", > >> + }, > >> + { > >> + "ArchStdEvent": "MEM_ACCESS_WR", > >> + }, > >> + { > >> + "ArchStdEvent": "UNALIGNED_LD_SPEC", > >> + }, > >> + { > >> + "ArchStdEvent": "UNALIGNED_ST_SPEC", > >> + }, > >> + { > >> + "ArchStdEvent": "UNALIGNED_LDST_SPEC", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_UNDEF", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_SVC", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_PABORT", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_DABORT", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_IRQ", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_FIQ", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_SMC", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_HVC", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_TRAP_PABORT", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_TRAP_DABORT", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_TRAP_OTHER", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_TRAP_IRQ", > >> + }, > >> + { > >> + "ArchStdEvent": "EXC_TRAP_FIQ", > >> + } > >> ] > >> -- > >> 2.9.4 > > thanks > Ganapat ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events 2018-07-31 17:29 ` Arnaldo Carvalho de Melo @ 2018-08-01 4:59 ` Ganapatrao Kulkarni -1 siblings, 0 replies; 11+ messages in thread From: Ganapatrao Kulkarni @ 2018-08-01 4:59 UTC (permalink / raw) To: linux-arm-kernel Hi Arnaldo, On Tue, Jul 31, 2018 at 10:59 PM, Arnaldo Carvalho de Melo <arnaldo.melo@gmail.com> wrote: > Em Tue, Jul 31, 2018 at 08:40:51PM +0530, Ganapatrao Kulkarni escreveu: >> Hi Arnaldo, >> >> On Tue, Jul 31, 2018 at 7:58 PM, Arnaldo Carvalho de Melo >> <arnaldo.melo@gmail.com> wrote: >> > Em Tue, Jul 31, 2018 at 03:32:51PM +0530, Ganapatrao Kulkarni escreveu: >> >> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> >> > >> > Can you please consider to provide an example of such counters being >> > used, i.e. with a simple C synthetic test that causes these events to >> > take place, then run it via 'perf stat' to show that indeed, they are >> > being programmed and read correctly? >> > >> > Ideally for all of them, but if that becomes too burdensome, for a few >> > of them? >> >> It may be tedious for all, certainly I will provide the test >> results/log for some of them(as many as possible). > > Right, we do try to test some of the events via 'perf test', for > instance: > > [root at jouet perf]# perf test openat > 2: Detect openat syscall event : Ok > 3: Detect openat syscall event on all cpus : Ok > 15: syscalls:sys_enter_openat event fields : Ok > [root at jouet perf]# we have not tried perf test, will look in to this test suite to keep it complaint on our hardware too! > > Things like setting up evsels for some events, then forking + calling a > syscall, then checking if that event appeared on the ring buffer, check > if the payload for the event, as read using the tracefs format fields > matches the parameters we passed in the syscall, etc. > > See tools/perf/tests/openat-syscall-tp-fields.c for that > "syscalls:sys_enter_openat event fields" specific source code. > > So doing some of these synthetic tests when updating the event files may > help us in the direction of having tests that run on those specific > hardwares (ThunderX2 in this case) everytime we run 'perf test', so that > we can detect failures sooner. > > I.e. first write a simple test for one of those events, use it as > documentation, at some point, as time permits, turn those into a 'perf > test' entry. All these events are implemented as per "ARMv8, The Performance Monitors Extension specification" [1]. Brief explanation of each of these events is already captured at tools/perf/pmu-events/arch/arm64/armv8-recommended.json [1] https://static.docs.arm.com/ddi0487/a/DDI0487A_j_armv8_arm.pdf?_ga=2.104377475.2065785066.1533095452-1490247355.1441251141 i have used ltp testcases as workload to test some of the events and log is below, root at SBR-26>ganapat>> perf stat -e unaligned_ld_spec,unaligned_st_spec,unaligned_ldst_spec,mem_access_rd,mem_access_wr,armv8_pmuv3_0/mem_access/ ltp/testcases/kernel/mem/mtest001 -p80 mtest01 0 TINFO : Total memory already used on system = 11849792 kbytes mtest01 0 TINFO : Total memory used needed to reach maximum = 214325040 kbytes mtest01 0 TINFO : Filling up 80% of ram which is 202475248 kbytes mtest01 1 TPASS : 202475248 kbytes allocated only. Performance counter stats for 'ltp/testcases/kernel/mem/mtest01/mtest01 -p80': 2,573 unaligned_ld_spec 3,976 unaligned_st_spec 6,549 unaligned_ldst_spec 1,525,489 mem_access_rd 1,549,531 mem_access_wr 3,075,020 armv8_pmuv3_0/mem_access/ 0.006368837 seconds time elapsed 0.000000000 seconds user 0.006390000 seconds sys root at SBR-26>ganapat>> perf stat -e l1d_cache_refill_rd,l1d_cache_refill_wr,armv8_pmuv3_0/l1d_cache_refill/ ./ltp/testcases/kernel/mem/mtest01/mtest01 -p80 mtest01 0 TINFO : Total memory already used on system = 11851520 kbytes mtest01 0 TINFO : Total memory used needed to reach maximum = 214325040 kbytes mtest01 0 TINFO : Filling up 80% of ram which is 202473520 kbytes mtest01 1 TPASS : 202473520 kbytes allocated only. Performance counter stats for './ltp/testcases/kernel/mem/mtest01/mtest01 -p80': 257,128 l1d_cache_refill_rd 162,151 l1d_cache_refill_wr 419,279 armv8_pmuv3_0/l1d_cache_refill/ 0.006118645 seconds time elapsed 0.000000000 seconds user 0.006141000 seconds sys root at SBR-26>ganapat>> perf stat -e exc_svc ./ltp/testcases/kernel/syscalls/brk/brk01 tst_test.c:1015: INFO: Timeout per run is 0h 05m 00s brk01.c:67: PASS: brk() works fine Summary: passed 1 failed 0 skipped 0 warnings 0 Performance counter stats for './ltp/testcases/kernel/syscalls/brk/brk01': 100 exc_svc 0.000887222 seconds time elapsed 0.000950000 seconds user 0.000000000 seconds sys root at SBR-26>ganapat>> > > Thanks, > > - Arnaldo > >> > >> > Thanks, >> > >> > - Arnaldo >> > >> >> --- >> >> .../arch/arm64/cavium/thunderx2/core-imp-def.json | 87 +++++++++++++++++++++- >> >> 1 file changed, 84 insertions(+), 3 deletions(-) >> >> >> >> diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json >> >> index bc03c06..752e47e 100644 >> >> --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json >> >> +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json >> >> @@ -12,6 +12,21 @@ >> >> "ArchStdEvent": "L1D_CACHE_REFILL_WR", >> >> }, >> >> { >> >> + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "L1D_CACHE_INVAL", >> >> + }, >> >> + { >> >> "ArchStdEvent": "L1D_TLB_REFILL_RD", >> >> }, >> >> { >> >> @@ -24,9 +39,75 @@ >> >> "ArchStdEvent": "L1D_TLB_WR", >> >> }, >> >> { >> >> + "ArchStdEvent": "L2D_TLB_REFILL_RD", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "L2D_TLB_REFILL_WR", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "L2D_TLB_RD", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "L2D_TLB_WR", >> >> + }, >> >> + { >> >> "ArchStdEvent": "BUS_ACCESS_RD", >> >> - }, >> >> - { >> >> + }, >> >> + { >> >> "ArchStdEvent": "BUS_ACCESS_WR", >> >> - } >> >> + }, >> >> + { >> >> + "ArchStdEvent": "MEM_ACCESS_RD", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "MEM_ACCESS_WR", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "UNALIGNED_LD_SPEC", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "UNALIGNED_ST_SPEC", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "UNALIGNED_LDST_SPEC", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_UNDEF", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_SVC", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_PABORT", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_DABORT", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_IRQ", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_FIQ", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_SMC", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_HVC", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_TRAP_PABORT", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_TRAP_DABORT", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_TRAP_OTHER", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_TRAP_IRQ", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_TRAP_FIQ", >> >> + } >> >> ] >> >> -- >> >> 2.9.4 >> >> thanks >> Ganapat thanks Ganapat ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events @ 2018-08-01 4:59 ` Ganapatrao Kulkarni 0 siblings, 0 replies; 11+ messages in thread From: Ganapatrao Kulkarni @ 2018-08-01 4:59 UTC (permalink / raw) To: Arnaldo Carvalho de Melo Cc: Ganapatrao Kulkarni, LKML, linux-arm-kernel, Alexander Shishkin, Jiri Olsa, namhyung, Peter Zijlstra, Ingo Molnar, Will Deacon, Mark Rutland, jnair, Robert Richter, Vadim.Lomovtsev, Jan.Glauber Hi Arnaldo, On Tue, Jul 31, 2018 at 10:59 PM, Arnaldo Carvalho de Melo <arnaldo.melo@gmail.com> wrote: > Em Tue, Jul 31, 2018 at 08:40:51PM +0530, Ganapatrao Kulkarni escreveu: >> Hi Arnaldo, >> >> On Tue, Jul 31, 2018 at 7:58 PM, Arnaldo Carvalho de Melo >> <arnaldo.melo@gmail.com> wrote: >> > Em Tue, Jul 31, 2018 at 03:32:51PM +0530, Ganapatrao Kulkarni escreveu: >> >> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> >> > >> > Can you please consider to provide an example of such counters being >> > used, i.e. with a simple C synthetic test that causes these events to >> > take place, then run it via 'perf stat' to show that indeed, they are >> > being programmed and read correctly? >> > >> > Ideally for all of them, but if that becomes too burdensome, for a few >> > of them? >> >> It may be tedious for all, certainly I will provide the test >> results/log for some of them(as many as possible). > > Right, we do try to test some of the events via 'perf test', for > instance: > > [root@jouet perf]# perf test openat > 2: Detect openat syscall event : Ok > 3: Detect openat syscall event on all cpus : Ok > 15: syscalls:sys_enter_openat event fields : Ok > [root@jouet perf]# we have not tried perf test, will look in to this test suite to keep it complaint on our hardware too! > > Things like setting up evsels for some events, then forking + calling a > syscall, then checking if that event appeared on the ring buffer, check > if the payload for the event, as read using the tracefs format fields > matches the parameters we passed in the syscall, etc. > > See tools/perf/tests/openat-syscall-tp-fields.c for that > "syscalls:sys_enter_openat event fields" specific source code. > > So doing some of these synthetic tests when updating the event files may > help us in the direction of having tests that run on those specific > hardwares (ThunderX2 in this case) everytime we run 'perf test', so that > we can detect failures sooner. > > I.e. first write a simple test for one of those events, use it as > documentation, at some point, as time permits, turn those into a 'perf > test' entry. All these events are implemented as per "ARMv8, The Performance Monitors Extension specification" [1]. Brief explanation of each of these events is already captured at tools/perf/pmu-events/arch/arm64/armv8-recommended.json [1] https://static.docs.arm.com/ddi0487/a/DDI0487A_j_armv8_arm.pdf?_ga=2.104377475.2065785066.1533095452-1490247355.1441251141 i have used ltp testcases as workload to test some of the events and log is below, root@SBR-26>ganapat>> perf stat -e unaligned_ld_spec,unaligned_st_spec,unaligned_ldst_spec,mem_access_rd,mem_access_wr,armv8_pmuv3_0/mem_access/ ltp/testcases/kernel/mem/mtest001 -p80 mtest01 0 TINFO : Total memory already used on system = 11849792 kbytes mtest01 0 TINFO : Total memory used needed to reach maximum = 214325040 kbytes mtest01 0 TINFO : Filling up 80% of ram which is 202475248 kbytes mtest01 1 TPASS : 202475248 kbytes allocated only. Performance counter stats for 'ltp/testcases/kernel/mem/mtest01/mtest01 -p80': 2,573 unaligned_ld_spec 3,976 unaligned_st_spec 6,549 unaligned_ldst_spec 1,525,489 mem_access_rd 1,549,531 mem_access_wr 3,075,020 armv8_pmuv3_0/mem_access/ 0.006368837 seconds time elapsed 0.000000000 seconds user 0.006390000 seconds sys root@SBR-26>ganapat>> perf stat -e l1d_cache_refill_rd,l1d_cache_refill_wr,armv8_pmuv3_0/l1d_cache_refill/ ./ltp/testcases/kernel/mem/mtest01/mtest01 -p80 mtest01 0 TINFO : Total memory already used on system = 11851520 kbytes mtest01 0 TINFO : Total memory used needed to reach maximum = 214325040 kbytes mtest01 0 TINFO : Filling up 80% of ram which is 202473520 kbytes mtest01 1 TPASS : 202473520 kbytes allocated only. Performance counter stats for './ltp/testcases/kernel/mem/mtest01/mtest01 -p80': 257,128 l1d_cache_refill_rd 162,151 l1d_cache_refill_wr 419,279 armv8_pmuv3_0/l1d_cache_refill/ 0.006118645 seconds time elapsed 0.000000000 seconds user 0.006141000 seconds sys root@SBR-26>ganapat>> perf stat -e exc_svc ./ltp/testcases/kernel/syscalls/brk/brk01 tst_test.c:1015: INFO: Timeout per run is 0h 05m 00s brk01.c:67: PASS: brk() works fine Summary: passed 1 failed 0 skipped 0 warnings 0 Performance counter stats for './ltp/testcases/kernel/syscalls/brk/brk01': 100 exc_svc 0.000887222 seconds time elapsed 0.000950000 seconds user 0.000000000 seconds sys root@SBR-26>ganapat>> > > Thanks, > > - Arnaldo > >> > >> > Thanks, >> > >> > - Arnaldo >> > >> >> --- >> >> .../arch/arm64/cavium/thunderx2/core-imp-def.json | 87 +++++++++++++++++++++- >> >> 1 file changed, 84 insertions(+), 3 deletions(-) >> >> >> >> diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json >> >> index bc03c06..752e47e 100644 >> >> --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json >> >> +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json >> >> @@ -12,6 +12,21 @@ >> >> "ArchStdEvent": "L1D_CACHE_REFILL_WR", >> >> }, >> >> { >> >> + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "L1D_CACHE_INVAL", >> >> + }, >> >> + { >> >> "ArchStdEvent": "L1D_TLB_REFILL_RD", >> >> }, >> >> { >> >> @@ -24,9 +39,75 @@ >> >> "ArchStdEvent": "L1D_TLB_WR", >> >> }, >> >> { >> >> + "ArchStdEvent": "L2D_TLB_REFILL_RD", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "L2D_TLB_REFILL_WR", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "L2D_TLB_RD", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "L2D_TLB_WR", >> >> + }, >> >> + { >> >> "ArchStdEvent": "BUS_ACCESS_RD", >> >> - }, >> >> - { >> >> + }, >> >> + { >> >> "ArchStdEvent": "BUS_ACCESS_WR", >> >> - } >> >> + }, >> >> + { >> >> + "ArchStdEvent": "MEM_ACCESS_RD", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "MEM_ACCESS_WR", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "UNALIGNED_LD_SPEC", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "UNALIGNED_ST_SPEC", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "UNALIGNED_LDST_SPEC", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_UNDEF", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_SVC", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_PABORT", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_DABORT", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_IRQ", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_FIQ", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_SMC", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_HVC", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_TRAP_PABORT", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_TRAP_DABORT", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_TRAP_OTHER", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_TRAP_IRQ", >> >> + }, >> >> + { >> >> + "ArchStdEvent": "EXC_TRAP_FIQ", >> >> + } >> >> ] >> >> -- >> >> 2.9.4 >> >> thanks >> Ganapat thanks Ganapat ^ permalink raw reply [flat|nested] 11+ messages in thread
* [tip:perf/core] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events 2018-07-31 10:02 ` Ganapatrao Kulkarni (?) (?) @ 2018-08-02 8:15 ` tip-bot for Ganapatrao Kulkarni -1 siblings, 0 replies; 11+ messages in thread From: tip-bot for Ganapatrao Kulkarni @ 2018-08-02 8:15 UTC (permalink / raw) To: linux-tip-commits Cc: alexander.shishkin, hpa, ganapatrao.kulkarni, acme, gklkml16, tglx, namhyung, linux-kernel, peterz, jnair, jan.glauber, jolsa, will.deacon, mark.rutland, vadim.lomovtsev, mingo, robert.richter Commit-ID: b9b77222d4ff6b5bb8f5d87fca20de0910618bb9 Gitweb: https://git.kernel.org/tip/b9b77222d4ff6b5bb8f5d87fca20de0910618bb9 Author: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> AuthorDate: Tue, 31 Jul 2018 15:32:51 +0530 Committer: Arnaldo Carvalho de Melo <acme@redhat.com> CommitDate: Tue, 31 Jul 2018 11:28:44 -0300 perf vendor events arm64: Update ThunderX2 implementation defined pmu core events Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ganapatrao Kulkarni <gklkml16@gmail.com> Cc: Jan Glauber <jan.glauber@cavium.com> Cc: Jayachandran C <jnair@caviumnetworks.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Robert Richter <robert.richter@cavium.com> Cc: Vadim Lomovtsev <vadim.lomovtsev@cavium.com> Cc: Will Deacon <will.deacon@arm.com> Link: http://lkml.kernel.org/r/20180731100251.23575-1-ganapatrao.kulkarni@cavium.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> --- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 87 +++++++++++++++++++++- 1 file changed, 84 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json index bc03c06c3918..752e47eb6977 100644 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json @@ -11,6 +11,21 @@ { "ArchStdEvent": "L1D_CACHE_REFILL_WR", }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL", + }, { "ArchStdEvent": "L1D_TLB_REFILL_RD", }, @@ -23,10 +38,76 @@ { "ArchStdEvent": "L1D_TLB_WR", }, + { + "ArchStdEvent": "L2D_TLB_REFILL_RD", + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_WR", + }, + { + "ArchStdEvent": "L2D_TLB_RD", + }, + { + "ArchStdEvent": "L2D_TLB_WR", + }, { "ArchStdEvent": "BUS_ACCESS_RD", - }, - { + }, + { "ArchStdEvent": "BUS_ACCESS_WR", - } + }, + { + "ArchStdEvent": "MEM_ACCESS_RD", + }, + { + "ArchStdEvent": "MEM_ACCESS_WR", + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC", + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC", + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC", + }, + { + "ArchStdEvent": "EXC_UNDEF", + }, + { + "ArchStdEvent": "EXC_SVC", + }, + { + "ArchStdEvent": "EXC_PABORT", + }, + { + "ArchStdEvent": "EXC_DABORT", + }, + { + "ArchStdEvent": "EXC_IRQ", + }, + { + "ArchStdEvent": "EXC_FIQ", + }, + { + "ArchStdEvent": "EXC_SMC", + }, + { + "ArchStdEvent": "EXC_HVC", + }, + { + "ArchStdEvent": "EXC_TRAP_PABORT", + }, + { + "ArchStdEvent": "EXC_TRAP_DABORT", + }, + { + "ArchStdEvent": "EXC_TRAP_OTHER", + }, + { + "ArchStdEvent": "EXC_TRAP_IRQ", + }, + { + "ArchStdEvent": "EXC_TRAP_FIQ", + } ] ^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-08-02 8:15 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-07-31 10:02 [PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events Ganapatrao Kulkarni 2018-07-31 10:02 ` Ganapatrao Kulkarni 2018-07-31 14:28 ` Arnaldo Carvalho de Melo 2018-07-31 14:28 ` Arnaldo Carvalho de Melo 2018-07-31 15:10 ` Ganapatrao Kulkarni 2018-07-31 15:10 ` Ganapatrao Kulkarni 2018-07-31 17:29 ` Arnaldo Carvalho de Melo 2018-07-31 17:29 ` Arnaldo Carvalho de Melo 2018-08-01 4:59 ` Ganapatrao Kulkarni 2018-08-01 4:59 ` Ganapatrao Kulkarni 2018-08-02 8:15 ` [tip:perf/core] " tip-bot for Ganapatrao Kulkarni
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