From: tony@atomide.com (Tony Lindgren)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
Date: Tue, 28 Aug 2018 09:25:56 -0700 [thread overview]
Message-ID: <20180828162556.GQ7523@atomide.com> (raw)
In-Reply-To: <20180828102642.26482-1-kishon@ti.com>
* Kishon Vijay Abraham I <kishon@ti.com> [180828 10:31]:
> AM65 has two PCIe controllers and each PCIe controller has '2' address
> spaces one within the 4GB address space of the SoC and the other above
> the 4GB address space of the SoC in addition to the register space. The
> size of the address space above the 4GB SoC address space is 4GB. These
> address ranges will be used by CPU/DMA to access the PCIe address space.
> In order to represent the address space above the 4GB SoC address space
> and to represent the size of this address space as 4GB, change
> address-cells and size-cells of interconnect to 2.
...
> cbass_mcu: interconnect at 28380000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
Yup great, the interconnect instances that don't need above 4GB
address space should stay this way.
Acked-by: Tony Lindgren <tony@atomide.com>
WARNING: multiple messages have this Message-ID (diff)
From: Tony Lindgren <tony@atomide.com>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>, Nishanth Menon <nm@ti.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Santosh Shilimkar <ssantosh@kernel.org>,
nsekhar@ti.com
Subject: Re: [PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
Date: Tue, 28 Aug 2018 09:25:56 -0700 [thread overview]
Message-ID: <20180828162556.GQ7523@atomide.com> (raw)
In-Reply-To: <20180828102642.26482-1-kishon@ti.com>
* Kishon Vijay Abraham I <kishon@ti.com> [180828 10:31]:
> AM65 has two PCIe controllers and each PCIe controller has '2' address
> spaces one within the 4GB address space of the SoC and the other above
> the 4GB address space of the SoC in addition to the register space. The
> size of the address space above the 4GB SoC address space is 4GB. These
> address ranges will be used by CPU/DMA to access the PCIe address space.
> In order to represent the address space above the 4GB SoC address space
> and to represent the size of this address space as 4GB, change
> address-cells and size-cells of interconnect to 2.
...
> cbass_mcu: interconnect@28380000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
Yup great, the interconnect instances that don't need above 4GB
address space should stay this way.
Acked-by: Tony Lindgren <tony@atomide.com>
next prev parent reply other threads:[~2018-08-28 16:25 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-28 10:26 [PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2 Kishon Vijay Abraham I
2018-08-28 10:26 ` Kishon Vijay Abraham I
2018-08-28 10:26 ` Kishon Vijay Abraham I
2018-08-28 16:25 ` Tony Lindgren [this message]
2018-08-28 16:25 ` Tony Lindgren
2018-08-31 15:26 ` Vignesh R
2018-08-31 15:26 ` Vignesh R
2018-08-31 15:26 ` Vignesh R
2018-09-01 2:44 ` Nishanth Menon
2018-09-01 2:44 ` Nishanth Menon
2018-09-01 2:44 ` Nishanth Menon
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