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From: Will Deacon <will.deacon@arm.com>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-crypto@vger.kernel.org, catalin.marinas@arm.com,
	herbert@gondor.apana.org.au, ebiggers@google.com,
	suzuki.poulose@arm.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/4] arm64: cpufeature: add feature for CRC32 instructions
Date: Tue, 28 Aug 2018 18:01:36 +0100	[thread overview]
Message-ID: <20180828170135.GC19825@arm.com> (raw)
In-Reply-To: <20180827110245.14812-3-ard.biesheuvel@linaro.org>

On Mon, Aug 27, 2018 at 01:02:43PM +0200, Ard Biesheuvel wrote:
> Add a CRC32 feature bit and wire it up to the CPU id register so we
> will be able to use alternatives patching for CRC32 operations.
> 
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  arch/arm64/include/asm/cpucaps.h | 3 ++-
>  arch/arm64/kernel/cpufeature.c   | 9 +++++++++
>  2 files changed, 11 insertions(+), 1 deletion(-)

Acked-by: Will Deacon <will.deacon@arm.com>

With the minor caveat below...

> diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
> index ae1f70450fb2..9932aca9704b 100644
> --- a/arch/arm64/include/asm/cpucaps.h
> +++ b/arch/arm64/include/asm/cpucaps.h
> @@ -51,7 +51,8 @@
>  #define ARM64_SSBD				30
>  #define ARM64_MISMATCHED_CACHE_TYPE		31
>  #define ARM64_HAS_STAGE2_FWB			32
> +#define ARM64_HAS_CRC32				33
>  
> -#define ARM64_NCAPS				33
> +#define ARM64_NCAPS				34


... if this goes via crypto, you'll almost certainly get a (trivial)
conflict with arm64, since these numbers get bumped all the time.

Will

>  #endif /* __ASM_CPUCAPS_H */
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index e238b7932096..7626b80128f5 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1222,6 +1222,15 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>  		.cpu_enable = cpu_enable_hw_dbm,
>  	},
>  #endif
> +	{
> +		.desc = "CRC32 instructions",
> +		.capability = ARM64_HAS_CRC32,
> +		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
> +		.matches = has_cpuid_feature,
> +		.sys_reg = SYS_ID_AA64ISAR0_EL1,
> +		.field_pos = ID_AA64ISAR0_CRC32_SHIFT,
> +		.min_field_value = 1,
> +	},
>  	{},
>  };
>  
> -- 
> 2.18.0
> 

WARNING: multiple messages have this Message-ID (diff)
From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/4] arm64: cpufeature: add feature for CRC32 instructions
Date: Tue, 28 Aug 2018 18:01:36 +0100	[thread overview]
Message-ID: <20180828170135.GC19825@arm.com> (raw)
In-Reply-To: <20180827110245.14812-3-ard.biesheuvel@linaro.org>

On Mon, Aug 27, 2018 at 01:02:43PM +0200, Ard Biesheuvel wrote:
> Add a CRC32 feature bit and wire it up to the CPU id register so we
> will be able to use alternatives patching for CRC32 operations.
> 
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  arch/arm64/include/asm/cpucaps.h | 3 ++-
>  arch/arm64/kernel/cpufeature.c   | 9 +++++++++
>  2 files changed, 11 insertions(+), 1 deletion(-)

Acked-by: Will Deacon <will.deacon@arm.com>

With the minor caveat below...

> diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
> index ae1f70450fb2..9932aca9704b 100644
> --- a/arch/arm64/include/asm/cpucaps.h
> +++ b/arch/arm64/include/asm/cpucaps.h
> @@ -51,7 +51,8 @@
>  #define ARM64_SSBD				30
>  #define ARM64_MISMATCHED_CACHE_TYPE		31
>  #define ARM64_HAS_STAGE2_FWB			32
> +#define ARM64_HAS_CRC32				33
>  
> -#define ARM64_NCAPS				33
> +#define ARM64_NCAPS				34


... if this goes via crypto, you'll almost certainly get a (trivial)
conflict with arm64, since these numbers get bumped all the time.

Will

>  #endif /* __ASM_CPUCAPS_H */
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index e238b7932096..7626b80128f5 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1222,6 +1222,15 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>  		.cpu_enable = cpu_enable_hw_dbm,
>  	},
>  #endif
> +	{
> +		.desc = "CRC32 instructions",
> +		.capability = ARM64_HAS_CRC32,
> +		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
> +		.matches = has_cpuid_feature,
> +		.sys_reg = SYS_ID_AA64ISAR0_EL1,
> +		.field_pos = ID_AA64ISAR0_CRC32_SHIFT,
> +		.min_field_value = 1,
> +	},
>  	{},
>  };
>  
> -- 
> 2.18.0
> 

  reply	other threads:[~2018-08-28 17:01 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-27 11:02 [PATCH 0/4] arm64: wire CRC32 instructions into core crc32 routines Ard Biesheuvel
2018-08-27 11:02 ` Ard Biesheuvel
2018-08-27 11:02 ` [PATCH 1/4] lib/crc32: make core crc32() routines weak so they can be overridden Ard Biesheuvel
2018-08-27 11:02   ` Ard Biesheuvel
2018-09-04  9:44   ` Herbert Xu
2018-09-04  9:44     ` Herbert Xu
2018-09-04  9:44     ` Herbert Xu
2018-08-27 11:02 ` [PATCH 2/4] arm64: cpufeature: add feature for CRC32 instructions Ard Biesheuvel
2018-08-27 11:02   ` Ard Biesheuvel
2018-08-28 17:01   ` Will Deacon [this message]
2018-08-28 17:01     ` Will Deacon
2018-08-28 18:43     ` Ard Biesheuvel
2018-08-28 18:43       ` Ard Biesheuvel
2018-09-04  3:18       ` Herbert Xu
2018-09-04  3:18         ` Herbert Xu
2018-09-04  9:38         ` Will Deacon
2018-09-04  9:38           ` Will Deacon
2018-09-04  9:44           ` Herbert Xu
2018-09-04  9:44             ` Herbert Xu
2018-09-10 15:45         ` Catalin Marinas
2018-09-10 15:45           ` Catalin Marinas
2018-08-27 11:02 ` [PATCH 3/4] arm64/lib: add accelerated crc32 routines Ard Biesheuvel
2018-08-27 11:02   ` Ard Biesheuvel
2018-08-27 11:02 ` [PATCH 4/4] crypto: arm64/crc32 - remove PMULL based CRC32 driver Ard Biesheuvel
2018-08-27 11:02   ` Ard Biesheuvel
2018-09-04  5:21   ` Herbert Xu
2018-09-04  5:21     ` Herbert Xu
2018-08-27 14:53 ` [PATCH 0/4] arm64: wire CRC32 instructions into core crc32 routines Theodore Y. Ts'o
2018-08-27 14:53   ` Theodore Y. Ts'o
2018-08-27 15:18   ` Ard Biesheuvel
2018-08-27 15:18     ` Ard Biesheuvel

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