[Qemu-devel] [PATCH v2 0/2] target/xtensa: convert to do_transaction_failed

[Qemu-devel] [PATCH v2 0/2] target/xtensa: convert to do_transaction_failed

[Max Filippov]

Hello,

this series converts target/xtensa to use do_transaction_failed callback
and adds a test that checks various types of access to the physically
unmapped addresses.

Changes v1->v2:
- change ldl_phys to address_space_ldl in get_pte and check transaction
  for success;
- add tests that attempt TLB autorefill from the physically unmapped
  addresses.

Max Filippov (2):
  target/xtensa: convert to do_transaction_failed
  tests/tcg/xtensa: add test for failed memory transactions

 target/xtensa/cpu.c              |   2 +-
 target/xtensa/cpu.h              |   7 ++-
 target/xtensa/helper.c           |  22 ++++++-
 target/xtensa/op_helper.c        |  12 ++--
 tests/tcg/xtensa/Makefile        |   1 +
 tests/tcg/xtensa/test_phys_mem.S | 124 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 156 insertions(+), 12 deletions(-)
 create mode 100644 tests/tcg/xtensa/test_phys_mem.S

-- 
2.11.0

[Qemu-devel] [PATCH v2 1/2] target/xtensa: convert to do_transaction_failed

[Max Filippov]

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
Changes v1->v2:
- change ldl_phys to address_space_ldl in get_pte and check transaction
  for success;

 target/xtensa/cpu.c       |  2 +-
 target/xtensa/cpu.h       |  7 ++++---
 target/xtensa/helper.c    | 22 +++++++++++++++++++---
 target/xtensa/op_helper.c | 12 +++++++-----
 4 files changed, 31 insertions(+), 12 deletions(-)

diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 590813d4f7b9..a54dbe42602d 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -186,7 +186,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
 #else
     cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
     cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
-    cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
+    cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
 #endif
     cc->debug_excp_handler = xtensa_breakpoint_handler;
     cc->disas_set_info = xtensa_cpu_disas_set_info;
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 7472cf3ca32a..1362772617ea 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -497,9 +497,10 @@ int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size,
                                 int mmu_idx);
 void xtensa_cpu_do_interrupt(CPUState *cpu);
 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
-void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
-                                     bool is_write, bool is_exec, int opaque,
-                                     unsigned size);
+void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
+                                      unsigned size, MMUAccessType access_type,
+                                      int mmu_idx, MemTxAttrs attrs,
+                                      MemTxResult response, uintptr_t retaddr);
 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
                            fprintf_function cpu_fprintf, int flags);
 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index f74636f67854..0484f5fab808 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -642,11 +642,27 @@ static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
     int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
             &paddr, &page_size, &access, false);
 
-    qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n",
-                  __func__, vaddr, ret ? ~0 : paddr);
+    if (ret == 0) {
+        qemu_log_mask(CPU_LOG_MMU,
+                      "%s: autorefill(%08x): PTE va = %08x, pa = %08x\n",
+                      __func__, vaddr, pt_vaddr, paddr);
+    } else {
+        qemu_log_mask(CPU_LOG_MMU,
+                      "%s: autorefill(%08x): PTE va = %08x, failed (%d)\n",
+                      __func__, vaddr, pt_vaddr, ret);
+    }
 
     if (ret == 0) {
-        *pte = ldl_phys(cs->as, paddr);
+        MemTxResult result;
+
+        *pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED,
+                                 &result);
+        if (result != MEMTX_OK) {
+            qemu_log_mask(CPU_LOG_MMU,
+                          "%s: couldn't load PTE: transaction failed (%u)\n",
+                          __func__, (unsigned)result);
+            ret = 1;
+        }
     }
     return ret;
 }
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
index d4c942d87980..06fe346f02ff 100644
--- a/target/xtensa/op_helper.c
+++ b/target/xtensa/op_helper.c
@@ -78,18 +78,20 @@ void tlb_fill(CPUState *cs, target_ulong vaddr, int size,
     }
 }
 
-void xtensa_cpu_do_unassigned_access(CPUState *cs, hwaddr addr,
-                                     bool is_write, bool is_exec, int opaque,
-                                     unsigned size)
+void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
+                                      unsigned size, MMUAccessType access_type,
+                                      int mmu_idx, MemTxAttrs attrs,
+                                      MemTxResult response, uintptr_t retaddr)
 {
     XtensaCPU *cpu = XTENSA_CPU(cs);
     CPUXtensaState *env = &cpu->env;
 
+    cpu_restore_state(cs, retaddr, true);
     HELPER(exception_cause_vaddr)(env, env->pc,
-                                  is_exec ?
+                                  access_type == MMU_INST_FETCH ?
                                   INSTR_PIF_ADDR_ERROR_CAUSE :
                                   LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
-                                  is_exec ? addr : cs->mem_io_vaddr);
+                                  addr);
 }
 
 static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
-- 
2.11.0

[Qemu-devel] [PATCH v2 2/2] tests/tcg/xtensa: add test for failed memory transactions

[Max Filippov]

Failed memory transactions should raise exceptions 14 (for fetch) or 15
(for load/store) with XEA2.

Memory accesses that result in TLB miss followed by an attempt to load
PTE from physical memory which fails should raise InstTLBMiss or
LoadStoreTLBMiss with XEA2.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
Changes v1->v2:
- add tests that attempt TLB autorefill from the physically unmapped
  addresses.

 tests/tcg/xtensa/Makefile        |   1 +
 tests/tcg/xtensa/test_phys_mem.S | 124 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 125 insertions(+)
 create mode 100644 tests/tcg/xtensa/test_phys_mem.S

diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile
index 091518c05583..2f5691f75b09 100644
--- a/tests/tcg/xtensa/Makefile
+++ b/tests/tcg/xtensa/Makefile
@@ -44,6 +44,7 @@ TESTCASES += test_mmu.tst
 TESTCASES += test_mul16.tst
 TESTCASES += test_mul32.tst
 TESTCASES += test_nsa.tst
+TESTCASES += test_phys_mem.tst
 ifdef XT
 TESTCASES += test_pipeline.tst
 endif
diff --git a/tests/tcg/xtensa/test_phys_mem.S b/tests/tcg/xtensa/test_phys_mem.S
new file mode 100644
index 000000000000..aae0a793a718
--- /dev/null
+++ b/tests/tcg/xtensa/test_phys_mem.S
@@ -0,0 +1,124 @@
+#include "macros.inc"
+
+test_suite phys_mem
+
+.purgem test_init
+
+.macro test_init
+    movi    a2, 0xc0000003 /* PPN */
+    movi    a3, 0xc0000004 /* VPN */
+    wdtlb   a2, a3
+    witlb   a2, a3
+    movi    a2, 0xc0000000
+    wsr     a2, ptevaddr
+.endm
+
+test inst_fetch_get_pte_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0x20000000
+    jx      a2
+2:
+    movi    a2, 0x20000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 16
+    assert  eq, a2, a3
+test_end
+
+test read_get_pte_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0x20000000
+1:
+    l32i    a3, a2, 0
+    test_fail
+2:
+    movi    a2, 0x20000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    movi    a2, 1b
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 24
+    assert  eq, a2, a3
+test_end
+
+test write_get_pte_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0x20000000
+1:
+    s32i    a3, a2, 0
+    test_fail
+2:
+    movi    a2, 0x20000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    movi    a2, 1b
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 24
+    assert  eq, a2, a3
+test_end
+
+test inst_fetch_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0xc0000000
+    jx      a2
+2:
+    movi    a2, 0xc0000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 14
+    assert  eq, a2, a3
+test_end
+
+test read_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0xc0000000
+1:
+    l32i    a3, a2, 0
+    test_fail
+2:
+    movi    a2, 0xc0000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    movi    a2, 1b
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 15
+    assert  eq, a2, a3
+test_end
+
+test write_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0xc0000000
+1:
+    s32i    a3, a2, 0
+    test_fail
+2:
+    movi    a2, 0xc0000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    movi    a2, 1b
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 15
+    assert  eq, a2, a3
+test_end
+
+test_suite_end
-- 
2.11.0