* [PATCH v1] arm64: dts: sdm845: enable tsens thermal zones
@ 2018-07-18 7:49 ` Amit Kucheria
0 siblings, 0 replies; 14+ messages in thread
From: Amit Kucheria @ 2018-07-18 7:49 UTC (permalink / raw)
To: linux-arm-kernel
One thermal zone per cpu is defined
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++++++++++++++++++++++++++++++++++
1 file changed, 170 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 01ff146..a75be7c 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -340,4 +340,174 @@
};
};
};
+
+ thermal-zones {
+ cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit0: trip1 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ cpu_alert1: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit1: trip1 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ cpu_alert2: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit2: trip1 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu3-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ cpu_alert3: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit3: trip1 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu4-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ cpu_alert4: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit4: trip1 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu5-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ cpu_alert5: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit5: trip1 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu6-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ cpu_alert6: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit6: trip1 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu7-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ cpu_alert7: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit7: trip1 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v1] arm64: dts: sdm845: enable tsens thermal zones
2018-07-18 7:49 ` Amit Kucheria
@ 2018-07-26 0:47 ` Matthias Kaehlcke
-1 siblings, 0 replies; 14+ messages in thread
From: Matthias Kaehlcke @ 2018-07-26 0:47 UTC (permalink / raw)
To: Amit Kucheria
Cc: linux-kernel, rnayak, linux-arm-msm, bjorn.andersson, andy.gross,
dianders, edubezval, David Brown, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, linux-soc, devicetree,
linux-arm-kernel
Hi Amit,
On Wed, Jul 18, 2018 at 01:19:17PM +0530, Amit Kucheria wrote:
> One thermal zone per cpu is defined
>
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++++++++++++++++++++++++++++++++++
> 1 file changed, 170 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 01ff146..a75be7c 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -340,4 +340,174 @@
> };
> };
> };
> +
> + thermal-zones {
> + cpu0-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
In the context of the TSENS patches you mentioned that you are working
on interrupt support. Can the polling delays be removed once that is merged?
> + thermal-sensors = <&tsens0 1>;
> +
> + trips {
> + cpu_alert0: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit0: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu1-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 2>;
> +
> + trips {
> + cpu_alert1: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit1: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu2-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 3>;
> +
> + trips {
> + cpu_alert2: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit2: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu3-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 4>;
> +
> + trips {
> + cpu_alert3: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit3: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu4-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 7>;
> +
> + trips {
> + cpu_alert4: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit4: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu5-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 8>;
> +
> + trips {
> + cpu_alert5: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit5: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu6-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 9>;
> +
> + trips {
> + cpu_alert6: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit6: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu7-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 10>;
> +
> + trips {
> + cpu_alert7: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit7: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
Dumb DT question: the trip information is the same for all CPUs. Would
it be possible to have a single node and refer to it with a phandle?
I suppose the anwer is no and even if it was possible we probably
wouldn't want it, since it would complicate overriding settings for a
specific CPU (should that ever be needed ...) or cluster. Just wondering.
> + };
> + };
> };
I don't have documentation to verify that the sensors and CPUs match,
but it is in line with what I've seen in some Android tree, so it
seems alright ;-)
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Tested-by: Matthias Kaehlcke <mka@chromium.org>
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v1] arm64: dts: sdm845: enable tsens thermal zones
@ 2018-07-26 0:47 ` Matthias Kaehlcke
0 siblings, 0 replies; 14+ messages in thread
From: Matthias Kaehlcke @ 2018-07-26 0:47 UTC (permalink / raw)
To: linux-arm-kernel
Hi Amit,
On Wed, Jul 18, 2018 at 01:19:17PM +0530, Amit Kucheria wrote:
> One thermal zone per cpu is defined
>
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++++++++++++++++++++++++++++++++++
> 1 file changed, 170 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 01ff146..a75be7c 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -340,4 +340,174 @@
> };
> };
> };
> +
> + thermal-zones {
> + cpu0-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
In the context of the TSENS patches you mentioned that you are working
on interrupt support. Can the polling delays be removed once that is merged?
> + thermal-sensors = <&tsens0 1>;
> +
> + trips {
> + cpu_alert0: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit0: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu1-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 2>;
> +
> + trips {
> + cpu_alert1: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit1: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu2-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 3>;
> +
> + trips {
> + cpu_alert2: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit2: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu3-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 4>;
> +
> + trips {
> + cpu_alert3: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit3: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu4-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 7>;
> +
> + trips {
> + cpu_alert4: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit4: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu5-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 8>;
> +
> + trips {
> + cpu_alert5: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit5: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu6-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 9>;
> +
> + trips {
> + cpu_alert6: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit6: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu7-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 10>;
> +
> + trips {
> + cpu_alert7: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit7: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
Dumb DT question: the trip information is the same for all CPUs. Would
it be possible to have a single node and refer to it with a phandle?
I suppose the anwer is no and even if it was possible we probably
wouldn't want it, since it would complicate overriding settings for a
specific CPU (should that ever be needed ...) or cluster. Just wondering.
> + };
> + };
> };
I don't have documentation to verify that the sensors and CPUs match,
but it is in line with what I've seen in some Android tree, so it
seems alright ;-)
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Tested-by: Matthias Kaehlcke <mka@chromium.org>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v1] arm64: dts: sdm845: enable tsens thermal zones
2018-07-26 0:47 ` Matthias Kaehlcke
@ 2018-07-26 10:16 ` Amit Kucheria
-1 siblings, 0 replies; 14+ messages in thread
From: Amit Kucheria @ 2018-07-26 10:16 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: LKML, Rajendra Nayak, linux-arm-msm, Bjorn Andersson, Andy Gross,
Douglas Anderson, Eduardo Valentin, David Brown, Rob Herring,
Mark Rutland, Catalin Marinas, Will Deacon,
open list:ARM/QUALCOMM SUPPORT,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, lakml
On Thu, Jul 26, 2018 at 6:17 AM, Matthias Kaehlcke <mka@chromium.org> wrote:
> Hi Amit,
>
> On Wed, Jul 18, 2018 at 01:19:17PM +0530, Amit Kucheria wrote:
>> One thermal zone per cpu is defined
>>
>> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
>> ---
>> arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 170 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> index 01ff146..a75be7c 100644
>> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> @@ -340,4 +340,174 @@
>> };
>> };
>> };
>> +
>> + thermal-zones {
>> + cpu0-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>
> In the context of the TSENS patches you mentioned that you are working
> on interrupt support. Can the polling delays be removed once that is merged?
Yes, that'd be the idea.
>
>> + thermal-sensors = <&tsens0 1>;
>> +
>> + trips {
>> + cpu_alert0: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit0: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + cpu1-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> +
>> + thermal-sensors = <&tsens0 2>;
>> +
>> + trips {
>> + cpu_alert1: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit1: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + cpu2-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> +
>> + thermal-sensors = <&tsens0 3>;
>> +
>> + trips {
>> + cpu_alert2: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit2: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + cpu3-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> +
>> + thermal-sensors = <&tsens0 4>;
>> +
>> + trips {
>> + cpu_alert3: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit3: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + cpu4-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> +
>> + thermal-sensors = <&tsens0 7>;
>> +
>> + trips {
>> + cpu_alert4: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit4: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + cpu5-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> +
>> + thermal-sensors = <&tsens0 8>;
>> +
>> + trips {
>> + cpu_alert5: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit5: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + cpu6-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> +
>> + thermal-sensors = <&tsens0 9>;
>> +
>> + trips {
>> + cpu_alert6: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit6: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + cpu7-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> +
>> + thermal-sensors = <&tsens0 10>;
>> +
>> + trips {
>> + cpu_alert7: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit7: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>
> Dumb DT question: the trip information is the same for all CPUs. Would
> it be possible to have a single node and refer to it with a phandle?
There is some work to do that for cooling maps, not for the actual
trip points though:
https://lore.kernel.org/lkml/cover.1530766981.git.viresh.kumar@linaro.org/T/#u
> I suppose the anwer is no and even if it was possible we probably
> wouldn't want it, since it would complicate overriding settings for a
> specific CPU (should that ever be needed ...) or cluster. Just wondering.
>
>> + };
>> + };
>> };
>
> I don't have documentation to verify that the sensors and CPUs match,
> but it is in line with what I've seen in some Android tree, so it
> seems alright ;-)
>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> Tested-by: Matthias Kaehlcke <mka@chromium.org>
Thanks Matthias.
Regards,
Amit
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v1] arm64: dts: sdm845: enable tsens thermal zones
@ 2018-07-26 10:16 ` Amit Kucheria
0 siblings, 0 replies; 14+ messages in thread
From: Amit Kucheria @ 2018-07-26 10:16 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 26, 2018 at 6:17 AM, Matthias Kaehlcke <mka@chromium.org> wrote:
> Hi Amit,
>
> On Wed, Jul 18, 2018 at 01:19:17PM +0530, Amit Kucheria wrote:
>> One thermal zone per cpu is defined
>>
>> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
>> ---
>> arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 170 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> index 01ff146..a75be7c 100644
>> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> @@ -340,4 +340,174 @@
>> };
>> };
>> };
>> +
>> + thermal-zones {
>> + cpu0-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>
> In the context of the TSENS patches you mentioned that you are working
> on interrupt support. Can the polling delays be removed once that is merged?
Yes, that'd be the idea.
>
>> + thermal-sensors = <&tsens0 1>;
>> +
>> + trips {
>> + cpu_alert0: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit0: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + cpu1-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> +
>> + thermal-sensors = <&tsens0 2>;
>> +
>> + trips {
>> + cpu_alert1: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit1: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + cpu2-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> +
>> + thermal-sensors = <&tsens0 3>;
>> +
>> + trips {
>> + cpu_alert2: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit2: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + cpu3-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> +
>> + thermal-sensors = <&tsens0 4>;
>> +
>> + trips {
>> + cpu_alert3: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit3: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + cpu4-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> +
>> + thermal-sensors = <&tsens0 7>;
>> +
>> + trips {
>> + cpu_alert4: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit4: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + cpu5-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> +
>> + thermal-sensors = <&tsens0 8>;
>> +
>> + trips {
>> + cpu_alert5: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit5: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + cpu6-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> +
>> + thermal-sensors = <&tsens0 9>;
>> +
>> + trips {
>> + cpu_alert6: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit6: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + cpu7-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> +
>> + thermal-sensors = <&tsens0 10>;
>> +
>> + trips {
>> + cpu_alert7: trip0 {
>> + temperature = <75000>;
>> + hysteresis = <2000>;
>> + type = "passive";
>> + };
>> +
>> + cpu_crit7: trip1 {
>> + temperature = <110000>;
>> + hysteresis = <1000>;
>> + type = "critical";
>> + };
>> + };
>
> Dumb DT question: the trip information is the same for all CPUs. Would
> it be possible to have a single node and refer to it with a phandle?
There is some work to do that for cooling maps, not for the actual
trip points though:
https://lore.kernel.org/lkml/cover.1530766981.git.viresh.kumar at linaro.org/T/#u
> I suppose the anwer is no and even if it was possible we probably
> wouldn't want it, since it would complicate overriding settings for a
> specific CPU (should that ever be needed ...) or cluster. Just wondering.
>
>> + };
>> + };
>> };
>
> I don't have documentation to verify that the sensors and CPUs match,
> but it is in line with what I've seen in some Android tree, so it
> seems alright ;-)
>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> Tested-by: Matthias Kaehlcke <mka@chromium.org>
Thanks Matthias.
Regards,
Amit
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1] arm64: dts: sdm845: enable tsens thermal zones
2018-07-18 7:49 ` Amit Kucheria
@ 2018-08-28 15:37 ` Amit Kucheria
-1 siblings, 0 replies; 14+ messages in thread
From: Amit Kucheria @ 2018-08-28 15:37 UTC (permalink / raw)
To: Andy Gross
Cc: Rajendra Nayak, linux-arm-msm, Bjorn Andersson, Douglas Anderson,
Matthias Kaehlcke, Eduardo Valentin, David Brown, Rob Herring,
Mark Rutland, Catalin Marinas, Will Deacon,
open list:ARM/QUALCOMM SUPPORT,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, lakml,
LKML
Andy,
Do you have any feedback for this patch?
Regards,
Amit
On Wed, Jul 18, 2018 at 1:19 PM, Amit Kucheria <amit.kucheria@linaro.org> wrote:
> One thermal zone per cpu is defined
>
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++++++++++++++++++++++++++++++++++
> 1 file changed, 170 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 01ff146..a75be7c 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -340,4 +340,174 @@
> };
> };
> };
> +
> + thermal-zones {
> + cpu0-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 1>;
> +
> + trips {
> + cpu_alert0: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit0: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu1-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 2>;
> +
> + trips {
> + cpu_alert1: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit1: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu2-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 3>;
> +
> + trips {
> + cpu_alert2: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit2: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu3-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 4>;
> +
> + trips {
> + cpu_alert3: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit3: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu4-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 7>;
> +
> + trips {
> + cpu_alert4: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit4: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu5-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 8>;
> +
> + trips {
> + cpu_alert5: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit5: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu6-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 9>;
> +
> + trips {
> + cpu_alert6: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit6: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu7-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 10>;
> +
> + trips {
> + cpu_alert7: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit7: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> + };
> };
> --
> 2.7.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v1] arm64: dts: sdm845: enable tsens thermal zones
@ 2018-08-28 15:37 ` Amit Kucheria
0 siblings, 0 replies; 14+ messages in thread
From: Amit Kucheria @ 2018-08-28 15:37 UTC (permalink / raw)
To: linux-arm-kernel
Andy,
Do you have any feedback for this patch?
Regards,
Amit
On Wed, Jul 18, 2018 at 1:19 PM, Amit Kucheria <amit.kucheria@linaro.org> wrote:
> One thermal zone per cpu is defined
>
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++++++++++++++++++++++++++++++++++
> 1 file changed, 170 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 01ff146..a75be7c 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -340,4 +340,174 @@
> };
> };
> };
> +
> + thermal-zones {
> + cpu0-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 1>;
> +
> + trips {
> + cpu_alert0: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit0: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu1-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 2>;
> +
> + trips {
> + cpu_alert1: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit1: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu2-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 3>;
> +
> + trips {
> + cpu_alert2: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit2: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu3-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 4>;
> +
> + trips {
> + cpu_alert3: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit3: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu4-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 7>;
> +
> + trips {
> + cpu_alert4: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit4: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu5-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 8>;
> +
> + trips {
> + cpu_alert5: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit5: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu6-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 9>;
> +
> + trips {
> + cpu_alert6: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit6: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu7-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 10>;
> +
> + trips {
> + cpu_alert7: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit7: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> + };
> };
> --
> 2.7.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1] arm64: dts: sdm845: enable tsens thermal zones
2018-07-18 7:49 ` Amit Kucheria
@ 2018-08-29 9:39 ` Daniel Lezcano
-1 siblings, 0 replies; 14+ messages in thread
From: Daniel Lezcano @ 2018-08-29 9:39 UTC (permalink / raw)
To: Amit Kucheria, linux-kernel
Cc: rnayak, linux-arm-msm, bjorn.andersson, andy.gross, dianders, mka,
edubezval, David Brown, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, linux-soc, devicetree,
linux-arm-kernel
On 18/07/2018 09:49, Amit Kucheria wrote:
> One thermal zone per cpu is defined
The thermal zones are very close, especially when the CPUs belong to the
same 'cluster'. Very likely the temperature will propagate from one core
to another core, so when one core reaches the trip0, there is good
chance the other cores will be close and cross the trip0 threshold too.
Having multiple thermal zones, one per CPU, may trigger an interrupts
storm with the passive polling timer delay.
Does this board have a cooling device per CPU also ?
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++++++++++++++++++++++++++++++++++
> 1 file changed, 170 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 01ff146..a75be7c 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -340,4 +340,174 @@
> };
> };
> };
> +
> + thermal-zones {
> + cpu0-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 1>;
> +
> + trips {
> + cpu_alert0: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit0: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu1-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 2>;
> +
> + trips {
> + cpu_alert1: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit1: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu2-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 3>;
> +
> + trips {
> + cpu_alert2: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit2: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu3-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 4>;
> +
> + trips {
> + cpu_alert3: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit3: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu4-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 7>;
> +
> + trips {
> + cpu_alert4: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit4: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu5-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 8>;
> +
> + trips {
> + cpu_alert5: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit5: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu6-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 9>;
> +
> + trips {
> + cpu_alert6: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit6: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu7-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 10>;
> +
> + trips {
> + cpu_alert7: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit7: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> + };
> };
>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v1] arm64: dts: sdm845: enable tsens thermal zones
@ 2018-08-29 9:39 ` Daniel Lezcano
0 siblings, 0 replies; 14+ messages in thread
From: Daniel Lezcano @ 2018-08-29 9:39 UTC (permalink / raw)
To: linux-arm-kernel
On 18/07/2018 09:49, Amit Kucheria wrote:
> One thermal zone per cpu is defined
The thermal zones are very close, especially when the CPUs belong to the
same 'cluster'. Very likely the temperature will propagate from one core
to another core, so when one core reaches the trip0, there is good
chance the other cores will be close and cross the trip0 threshold too.
Having multiple thermal zones, one per CPU, may trigger an interrupts
storm with the passive polling timer delay.
Does this board have a cooling device per CPU also ?
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++++++++++++++++++++++++++++++++++
> 1 file changed, 170 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 01ff146..a75be7c 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -340,4 +340,174 @@
> };
> };
> };
> +
> + thermal-zones {
> + cpu0-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 1>;
> +
> + trips {
> + cpu_alert0: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit0: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu1-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 2>;
> +
> + trips {
> + cpu_alert1: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit1: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu2-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 3>;
> +
> + trips {
> + cpu_alert2: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit2: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu3-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 4>;
> +
> + trips {
> + cpu_alert3: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit3: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu4-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 7>;
> +
> + trips {
> + cpu_alert4: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit4: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu5-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 8>;
> +
> + trips {
> + cpu_alert5: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit5: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu6-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 9>;
> +
> + trips {
> + cpu_alert6: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit6: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu7-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens0 10>;
> +
> + trips {
> + cpu_alert7: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit7: trip1 {
> + temperature = <110000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> + };
> };
>
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v1] arm64: dts: sdm845: enable tsens thermal zones
2018-08-29 9:39 ` Daniel Lezcano
@ 2018-08-29 18:12 ` Matthias Kaehlcke
-1 siblings, 0 replies; 14+ messages in thread
From: Matthias Kaehlcke @ 2018-08-29 18:12 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Amit Kucheria, linux-kernel, rnayak, linux-arm-msm,
bjorn.andersson, andy.gross, dianders, edubezval, David Brown,
Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
linux-soc, devicetree, linux-arm-kernel, Taniya Das
On Wed, Aug 29, 2018 at 11:39:12AM +0200, Daniel Lezcano wrote:
> On 18/07/2018 09:49, Amit Kucheria wrote:
> > One thermal zone per cpu is defined
>
> The thermal zones are very close, especially when the CPUs belong to the
> same 'cluster'. Very likely the temperature will propagate from one core
> to another core, so when one core reaches the trip0, there is good
> chance the other cores will be close and cross the trip0 threshold too.
>
> Having multiple thermal zones, one per CPU, may trigger an interrupts
> storm with the passive polling timer delay.
>
> Does this board have a cooling device per CPU also ?
The cpufreq driver is still under development:
https://lore.kernel.org/patchwork/patch/966833/ . It currently doesn't
register cooling devices, but since CPUs from a 'cluster' use the same
cpufreq policy I think there will be one cooling device per 'cluster'.
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v1] arm64: dts: sdm845: enable tsens thermal zones
@ 2018-08-29 18:12 ` Matthias Kaehlcke
0 siblings, 0 replies; 14+ messages in thread
From: Matthias Kaehlcke @ 2018-08-29 18:12 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Aug 29, 2018 at 11:39:12AM +0200, Daniel Lezcano wrote:
> On 18/07/2018 09:49, Amit Kucheria wrote:
> > One thermal zone per cpu is defined
>
> The thermal zones are very close, especially when the CPUs belong to the
> same 'cluster'. Very likely the temperature will propagate from one core
> to another core, so when one core reaches the trip0, there is good
> chance the other cores will be close and cross the trip0 threshold too.
>
> Having multiple thermal zones, one per CPU, may trigger an interrupts
> storm with the passive polling timer delay.
>
> Does this board have a cooling device per CPU also ?
The cpufreq driver is still under development:
https://lore.kernel.org/patchwork/patch/966833/ . It currently doesn't
register cooling devices, but since CPUs from a 'cluster' use the same
cpufreq policy I think there will be one cooling device per 'cluster'.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1] arm64: dts: sdm845: enable tsens thermal zones
2018-08-29 9:39 ` Daniel Lezcano
@ 2018-08-30 5:25 ` Amit Kucheria
-1 siblings, 0 replies; 14+ messages in thread
From: Amit Kucheria @ 2018-08-30 5:25 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Linux Kernel Mailing List, Rajendra Nayak, linux-arm-msm,
Bjorn Andersson, Andy Gross, Doug Anderson, mka, Eduardo Valentin,
David Brown, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, open list:ARM/QUALCOMM SUPPORT, DTML, Lists LAKML
On Wed, Aug 29, 2018 at 3:09 PM Daniel Lezcano
<daniel.lezcano@linaro.org> wrote:
>
> On 18/07/2018 09:49, Amit Kucheria wrote:
> > One thermal zone per cpu is defined
>
> The thermal zones are very close, especially when the CPUs belong to the
> same 'cluster'. Very likely the temperature will propagate from one core
> to another core, so when one core reaches the trip0, there is good
> chance the other cores will be close and cross the trip0 threshold too.
Agreed. Once we have all the thermal and cpufreq bits in place, I'd
like to examine optimisations such as a virtual sensor, using the
coefficients to add weights, etc.
> Having multiple thermal zones, one per CPU, may trigger an interrupts
> storm with the passive polling timer delay.
I'm working on irq support for tsens that should alleviate that.
> Does this board have a cooling device per CPU also ?
As Matthias mentioned, DVFS is per cluster (4 cpus to a cluster).
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v1] arm64: dts: sdm845: enable tsens thermal zones
@ 2018-08-30 5:25 ` Amit Kucheria
0 siblings, 0 replies; 14+ messages in thread
From: Amit Kucheria @ 2018-08-30 5:25 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Aug 29, 2018 at 3:09 PM Daniel Lezcano
<daniel.lezcano@linaro.org> wrote:
>
> On 18/07/2018 09:49, Amit Kucheria wrote:
> > One thermal zone per cpu is defined
>
> The thermal zones are very close, especially when the CPUs belong to the
> same 'cluster'. Very likely the temperature will propagate from one core
> to another core, so when one core reaches the trip0, there is good
> chance the other cores will be close and cross the trip0 threshold too.
Agreed. Once we have all the thermal and cpufreq bits in place, I'd
like to examine optimisations such as a virtual sensor, using the
coefficients to add weights, etc.
> Having multiple thermal zones, one per CPU, may trigger an interrupts
> storm with the passive polling timer delay.
I'm working on irq support for tsens that should alleviate that.
> Does this board have a cooling device per CPU also ?
As Matthias mentioned, DVFS is per cluster (4 cpus to a cluster).
^ permalink raw reply [flat|nested] 14+ messages in thread