From: greg@kroah.com (Greg KH)
To: linux-arm-kernel@lists.infradead.org
Subject: [stable PATCH 1/2] arm64: Fix mismatched cache line size detection
Date: Wed, 12 Sep 2018 21:38:16 +0200 [thread overview]
Message-ID: <20180912193816.GF21563@kroah.com> (raw)
In-Reply-To: <1536052210-11625-1-git-send-email-suzuki.poulose@arm.com>
On Tue, Sep 04, 2018 at 10:10:09AM +0100, Suzuki K Poulose wrote:
> commit 4c4a39dd5fe2d13e2d2fa5fceb8ef95d19fc389a upstream
>
> If there is a mismatch in the I/D min line size, we must
> always use the system wide safe value both in applications
> and in the kernel, while performing cache operations. However,
> we have been checking more bits than just the min line sizes,
> which triggers false negatives. We may need to trap the user
> accesses in such cases, but not necessarily patch the kernel.
>
> This patch fixes the check to do the right thing as advertised.
> A new capability will be added to check mismatches in other
> fields and ensure we trap the CTR accesses.
>
> Fixes: be68a8aaf925 ("arm64: cpufeature: Fix CTR_EL0 field definitions")
> Cc: <stable@vger.kernel.org> # v4.9
Why 4.9? be68a8aaf925 only showed up in 4.16 and was backported only to
4.14-stable. Not to 4.9-stable from what I can tell.
thanks,
greg k-h
WARNING: multiple messages have this Message-ID (diff)
From: Greg KH <greg@kroah.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: stable@vger.kernel.org, will.deacon@arm.com,
mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, catalin.marinas@arm.com
Subject: Re: [stable PATCH 1/2] arm64: Fix mismatched cache line size detection
Date: Wed, 12 Sep 2018 21:38:16 +0200 [thread overview]
Message-ID: <20180912193816.GF21563@kroah.com> (raw)
In-Reply-To: <1536052210-11625-1-git-send-email-suzuki.poulose@arm.com>
On Tue, Sep 04, 2018 at 10:10:09AM +0100, Suzuki K Poulose wrote:
> commit 4c4a39dd5fe2d13e2d2fa5fceb8ef95d19fc389a upstream
>
> If there is a mismatch in the I/D min line size, we must
> always use the system wide safe value both in applications
> and in the kernel, while performing cache operations. However,
> we have been checking more bits than just the min line sizes,
> which triggers false negatives. We may need to trap the user
> accesses in such cases, but not necessarily patch the kernel.
>
> This patch fixes the check to do the right thing as advertised.
> A new capability will be added to check mismatches in other
> fields and ensure we trap the CTR accesses.
>
> Fixes: be68a8aaf925 ("arm64: cpufeature: Fix CTR_EL0 field definitions")
> Cc: <stable@vger.kernel.org> # v4.9
Why 4.9? be68a8aaf925 only showed up in 4.16 and was backported only to
4.14-stable. Not to 4.9-stable from what I can tell.
thanks,
greg k-h
next prev parent reply other threads:[~2018-09-12 19:38 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-04 9:10 [stable PATCH 1/2] arm64: Fix mismatched cache line size detection Suzuki K Poulose
2018-09-04 9:10 ` Suzuki K Poulose
2018-09-04 9:10 ` [stable PATCH 2/2] arm64: Handle mismatched cache type Suzuki K Poulose
2018-09-04 9:10 ` Suzuki K Poulose
2018-09-12 19:38 ` Greg KH
2018-09-12 19:38 ` Greg KH
2018-09-12 19:38 ` Greg KH [this message]
2018-09-12 19:38 ` [stable PATCH 1/2] arm64: Fix mismatched cache line size detection Greg KH
2018-09-13 9:54 ` Suzuki K Poulose
2018-09-13 9:54 ` Suzuki K Poulose
2018-09-13 12:19 ` Greg KH
2018-09-13 12:19 ` Greg KH
2018-09-13 12:40 ` Greg KH
2018-09-13 12:40 ` Greg KH
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