From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/4] drm/i915: Do not modifiy reserved bit in gens that do not have IPC
Date: Thu, 13 Sep 2018 14:46:45 -0700 [thread overview]
Message-ID: <20180913214645.GJ24668@intel.com> (raw)
In-Reply-To: <20180913212251.22283-3-jose.souza@intel.com>
On Thu, Sep 13, 2018 at 02:22:50PM -0700, José Roberto de Souza wrote:
> IPC was only added in SKL+(actually we don't even enable for SKL due
> WA) so without this change, driver was writing to a reserved bit.
>
> Also check for the WA in intel_init_ipc() to avoid further writes to
> ipc_enabled.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d99e5fabe93c..b2328f7d277d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6108,10 +6108,8 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
> u32 val;
>
> /* Display WA #0477 WaDisableIPC: skl */
> - if (IS_SKYLAKE(dev_priv)) {
> - dev_priv->ipc_enabled = false;
> + if (!HAS_IPC(dev_priv) || IS_SKYLAKE(dev_priv))
> return;
> - }
>
> val = I915_READ(DISP_ARB_CTL2);
>
> @@ -6126,7 +6124,9 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
> void intel_init_ipc(struct drm_i915_private *dev_priv)
> {
> dev_priv->ipc_enabled = false;
> - if (!HAS_IPC(dev_priv))
> +
> + /* Display WA #0477 WaDisableIPC: skl */
What about move the WA 0477 inside HAS_IPC and avoid the
duplication?
> + if (!HAS_IPC(dev_priv) || IS_SKYLAKE(dev_priv))
> return;
>
> dev_priv->ipc_enabled = true;
> --
> 2.19.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2018-09-13 21:47 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-13 21:22 [PATCH 1/4] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake José Roberto de Souza
2018-09-13 21:22 ` [PATCH 2/4] drm/i915: Unset reset pch handshake when PCH is not present in one place José Roberto de Souza
2018-09-13 21:51 ` Rodrigo Vivi
2018-09-14 0:46 ` Souza, Jose
2018-09-13 21:22 ` [PATCH 3/4] drm/i915: Do not modifiy reserved bit in gens that do not have IPC José Roberto de Souza
2018-09-13 21:46 ` Rodrigo Vivi [this message]
2018-09-13 21:22 ` [PATCH 4/4] drm/i915: Remove duplicated definition of intel_update_rawclk José Roberto de Souza
2018-09-13 21:47 ` Rodrigo Vivi
2018-09-13 21:41 ` [PATCH 1/4] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake Rodrigo Vivi
2018-09-13 22:30 ` ✗ Fi.CI.BAT: failure for series starting with [1/4] " Patchwork
2018-09-14 12:17 ` [PATCH 1/4] " Ville Syrjälä
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180913214645.GJ24668@intel.com \
--to=rodrigo.vivi@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jose.souza@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.