From: "Luck, Tony" <tony.luck@intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>,
Tony Luck <tony.luck@intel.com>,
Aristeu Rozanski <aris@redhat.com>,
Mauro Carvalho Chehab <mchehab@s-opensource.com>,
linux-edac@vger.kernel.org
Subject: [2/5] x86/mce: Add macors for corrected error count bit field
Date: Mon, 24 Sep 2018 13:16:10 -0700 [thread overview]
Message-ID: <20180924201613.14070-3-tony.luck@intel.com> (raw)
From: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
The bit field 52:38 of MCi_STATUS is for corrected error count.
Add {*_SHIFT|*_MASK|*_CEC(c)} macros for the bit field.
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
arch/x86/include/asm/mce.h | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index d53e5dd7471a..a81a22e3592c 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -30,15 +30,18 @@
#define MCG_EXT_CTL_LMCE_EN BIT_ULL(0) /* Enable LMCE */
/* MCi_STATUS register defines */
-#define MCI_STATUS_VAL BIT_ULL(63) /* valid error */
-#define MCI_STATUS_OVER BIT_ULL(62) /* previous errors lost */
-#define MCI_STATUS_UC BIT_ULL(61) /* uncorrected error */
-#define MCI_STATUS_EN BIT_ULL(60) /* error enabled */
-#define MCI_STATUS_MISCV BIT_ULL(59) /* misc error reg. valid */
-#define MCI_STATUS_ADDRV BIT_ULL(58) /* addr reg. valid */
-#define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */
-#define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */
-#define MCI_STATUS_AR BIT_ULL(55) /* Action required */
+#define MCI_STATUS_VAL BIT_ULL(63) /* valid error */
+#define MCI_STATUS_OVER BIT_ULL(62) /* previous errors lost */
+#define MCI_STATUS_UC BIT_ULL(61) /* uncorrected error */
+#define MCI_STATUS_EN BIT_ULL(60) /* error enabled */
+#define MCI_STATUS_MISCV BIT_ULL(59) /* misc error reg. valid */
+#define MCI_STATUS_ADDRV BIT_ULL(58) /* addr reg. valid */
+#define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */
+#define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */
+#define MCI_STATUS_AR BIT_ULL(55) /* Action required */
+#define MCI_STATUS_CEC_SHIFT 38 /* Corrected Error Count */
+#define MCI_STATUS_CEC_MASK 0x1fffc000000000ULL
+#define MCI_STATUS_CEC(c) (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
/* AMD-specific bits */
#define MCI_STATUS_TCC BIT_ULL(55) /* Task context corrupt */
next reply other threads:[~2018-09-24 20:16 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-24 20:16 Luck, Tony [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-09-24 20:24 [2/5] x86/mce: Add macors for corrected error count bit field Borislav Petkov
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