* [PATCH 1/2] dt-bindings: crypto: hip07-sec, drop incorrect commas
@ 2018-09-12 16:07 ` Jonathan Cameron
0 siblings, 0 replies; 8+ messages in thread
From: Jonathan Cameron @ 2018-09-12 16:07 UTC (permalink / raw)
To: linux-crypto, Rob Herring
Cc: devicetree, linux-arm-kernel, xuwei, Jonathan Cameron
There should not be a comma in the address used for the instance
so drop them.
This is a left over from a review of the final version before
Herbert Xu picked the series up.
Reported-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Fixes: 8f026dc887fe ("dt-bindings: Add bidnings for Hisilicon SEC crypto accelerators")
---
.../devicetree/bindings/crypto/hisilicon,hip07-sec.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt b/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt
index 78d2db9d4de5..d28fd1af01b4 100644
--- a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt
+++ b/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt
@@ -24,7 +24,7 @@ Optional properties:
Example:
-p1_sec_a: crypto@400,d2000000 {
+p1_sec_a: crypto@400d2000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x400 0xd0000000 0x0 0x10000
0x400 0xd2000000 0x0 0x10000
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 1/2] dt-bindings: crypto: hip07-sec, drop incorrect commas @ 2018-09-12 16:07 ` Jonathan Cameron 0 siblings, 0 replies; 8+ messages in thread From: Jonathan Cameron @ 2018-09-12 16:07 UTC (permalink / raw) To: linux-crypto, Rob Herring Cc: devicetree, linux-arm-kernel, xuwei, Jonathan Cameron There should not be a comma in the address used for the instance so drop them. This is a left over from a review of the final version before Herbert Xu picked the series up. Reported-by: Rob Herring <robh+dt@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Fixes: 8f026dc887fe ("dt-bindings: Add bidnings for Hisilicon SEC crypto accelerators") --- .../devicetree/bindings/crypto/hisilicon,hip07-sec.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt b/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt index 78d2db9d4de5..d28fd1af01b4 100644 --- a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt +++ b/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt @@ -24,7 +24,7 @@ Optional properties: Example: -p1_sec_a: crypto@400,d2000000 { +p1_sec_a: crypto@400d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x400 0xd0000000 0x0 0x10000 0x400 0xd2000000 0x0 0x10000 -- 2.18.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 1/2] dt-bindings: crypto: hip07-sec, drop incorrect commas @ 2018-09-12 16:07 ` Jonathan Cameron 0 siblings, 0 replies; 8+ messages in thread From: Jonathan Cameron @ 2018-09-12 16:07 UTC (permalink / raw) To: linux-arm-kernel There should not be a comma in the address used for the instance so drop them. This is a left over from a review of the final version before Herbert Xu picked the series up. Reported-by: Rob Herring <robh+dt@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Fixes: 8f026dc887fe ("dt-bindings: Add bidnings for Hisilicon SEC crypto accelerators") --- .../devicetree/bindings/crypto/hisilicon,hip07-sec.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt b/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt index 78d2db9d4de5..d28fd1af01b4 100644 --- a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt +++ b/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt @@ -24,7 +24,7 @@ Optional properties: Example: -p1_sec_a: crypto at 400,d2000000 { +p1_sec_a: crypto at 400d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x400 0xd0000000 0x0 0x10000 0x400 0xd2000000 0x0 0x10000 -- 2.18.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] arm64: dts: hisilicon hip07: drop commas from @address node names 2018-09-12 16:07 ` Jonathan Cameron (?) @ 2018-09-12 16:07 ` Jonathan Cameron -1 siblings, 0 replies; 8+ messages in thread From: Jonathan Cameron @ 2018-09-12 16:07 UTC (permalink / raw) To: linux-crypto, Rob Herring Cc: devicetree, linux-arm-kernel, xuwei, Jonathan Cameron Reported-by: Rob Herring <robh+dt@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Fixes: e4a1f7858ab8 ("arm64: dts: hisi: add SEC crypto accelerator nodes for hip07 SoC") --- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 28 ++++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index c33adefc3061..bc0113445655 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -949,35 +949,35 @@ reg = <0x0 0xc6000000 0x0 0x40000>; }; - p0_its_dsa_b: interrupt-controller@8,c6000000 { + p0_its_dsa_b: interrupt-controller@8c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x8 0xc6000000 0x0 0x40000>; }; - p1_its_peri_a: interrupt-controller@400,4c000000 { + p1_its_peri_a: interrupt-controller@4004c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x4c000000 0x0 0x40000>; }; - p1_its_peri_b: interrupt-controller@400,6c000000 { + p1_its_peri_b: interrupt-controller@4006c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x6c000000 0x0 0x40000>; }; - p1_its_dsa_a: interrupt-controller@400,c6000000 { + p1_its_dsa_a: interrupt-controller@400c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0xc6000000 0x0 0x40000>; }; - p1_its_dsa_b: interrupt-controller@408,c6000000 { + p1_its_dsa_b: interrupt-controller@408c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; @@ -1066,7 +1066,7 @@ num-pins = <3>; }; }; - p0_mbigen_alg_b:interrupt-controller@8,d0080000 { + p0_mbigen_alg_b:interrupt-controller@8d0080000 { compatible = "hisilicon,mbigen-v2"; reg = <0x8 0xd0080000 0x0 0x10000>; @@ -1083,7 +1083,7 @@ num-pins = <3>; }; }; - p1_mbigen_alg_a:interrupt-controller@400,d0080000 { + p1_mbigen_alg_a:interrupt-controller@400d0080000 { compatible = "hisilicon,mbigen-v2"; reg = <0x400 0xd0080000 0x0 0x10000>; @@ -1100,7 +1100,7 @@ num-pins = <3>; }; }; - p1_mbigen_alg_b:interrupt-controller@408,d0080000 { + p1_mbigen_alg_b:interrupt-controller@408d0080000 { compatible = "hisilicon,mbigen-v2"; reg = <0x408 0xd0080000 0x0 0x10000>; @@ -1187,7 +1187,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p0_smmu_alg_b: smmu_alg@8,d0040000 { + p0_smmu_alg_b: smmu_alg@8d0040000 { compatible = "arm,smmu-v3"; reg = <0x8 0xd0040000 0x0 0x20000>; interrupt-parent = <&p0_mbigen_smmu_alg_b>; @@ -1200,7 +1200,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_a: smmu_alg@400,d0040000 { + p1_smmu_alg_a: smmu_alg@400d0040000 { compatible = "arm,smmu-v3"; reg = <0x400 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_a>; @@ -1213,7 +1213,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_b: smmu_alg@408,d0040000 { + p1_smmu_alg_b: smmu_alg@408d0040000 { compatible = "arm,smmu-v3"; reg = <0x408 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_b>; @@ -1763,7 +1763,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p0_sec_b: crypto@8,d2000000 { + p0_sec_b: crypto@8d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x8 0xd0000000 0x0 0x10000 0x8 0xd2000000 0x0 0x10000 @@ -1804,7 +1804,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p1_sec_a: crypto@400,d2000000 { + p1_sec_a: crypto@400d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x400 0xd0000000 0x0 0x10000 0x400 0xd2000000 0x0 0x10000 @@ -1845,7 +1845,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p1_sec_b: crypto@408,d2000000 { + p1_sec_b: crypto@408d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x408 0xd0000000 0x0 0x10000 0x408 0xd2000000 0x0 0x10000 -- 2.18.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] arm64: dts: hisilicon hip07: drop commas from @address node names @ 2018-09-12 16:07 ` Jonathan Cameron 0 siblings, 0 replies; 8+ messages in thread From: Jonathan Cameron @ 2018-09-12 16:07 UTC (permalink / raw) To: linux-crypto, Rob Herring Cc: devicetree, linux-arm-kernel, xuwei, Jonathan Cameron Reported-by: Rob Herring <robh+dt@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Fixes: e4a1f7858ab8 ("arm64: dts: hisi: add SEC crypto accelerator nodes for hip07 SoC") --- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 28 ++++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index c33adefc3061..bc0113445655 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -949,35 +949,35 @@ reg = <0x0 0xc6000000 0x0 0x40000>; }; - p0_its_dsa_b: interrupt-controller@8,c6000000 { + p0_its_dsa_b: interrupt-controller@8c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x8 0xc6000000 0x0 0x40000>; }; - p1_its_peri_a: interrupt-controller@400,4c000000 { + p1_its_peri_a: interrupt-controller@4004c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x4c000000 0x0 0x40000>; }; - p1_its_peri_b: interrupt-controller@400,6c000000 { + p1_its_peri_b: interrupt-controller@4006c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x6c000000 0x0 0x40000>; }; - p1_its_dsa_a: interrupt-controller@400,c6000000 { + p1_its_dsa_a: interrupt-controller@400c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0xc6000000 0x0 0x40000>; }; - p1_its_dsa_b: interrupt-controller@408,c6000000 { + p1_its_dsa_b: interrupt-controller@408c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; @@ -1066,7 +1066,7 @@ num-pins = <3>; }; }; - p0_mbigen_alg_b:interrupt-controller@8,d0080000 { + p0_mbigen_alg_b:interrupt-controller@8d0080000 { compatible = "hisilicon,mbigen-v2"; reg = <0x8 0xd0080000 0x0 0x10000>; @@ -1083,7 +1083,7 @@ num-pins = <3>; }; }; - p1_mbigen_alg_a:interrupt-controller@400,d0080000 { + p1_mbigen_alg_a:interrupt-controller@400d0080000 { compatible = "hisilicon,mbigen-v2"; reg = <0x400 0xd0080000 0x0 0x10000>; @@ -1100,7 +1100,7 @@ num-pins = <3>; }; }; - p1_mbigen_alg_b:interrupt-controller@408,d0080000 { + p1_mbigen_alg_b:interrupt-controller@408d0080000 { compatible = "hisilicon,mbigen-v2"; reg = <0x408 0xd0080000 0x0 0x10000>; @@ -1187,7 +1187,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p0_smmu_alg_b: smmu_alg@8,d0040000 { + p0_smmu_alg_b: smmu_alg@8d0040000 { compatible = "arm,smmu-v3"; reg = <0x8 0xd0040000 0x0 0x20000>; interrupt-parent = <&p0_mbigen_smmu_alg_b>; @@ -1200,7 +1200,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_a: smmu_alg@400,d0040000 { + p1_smmu_alg_a: smmu_alg@400d0040000 { compatible = "arm,smmu-v3"; reg = <0x400 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_a>; @@ -1213,7 +1213,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_b: smmu_alg@408,d0040000 { + p1_smmu_alg_b: smmu_alg@408d0040000 { compatible = "arm,smmu-v3"; reg = <0x408 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_b>; @@ -1763,7 +1763,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p0_sec_b: crypto@8,d2000000 { + p0_sec_b: crypto@8d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x8 0xd0000000 0x0 0x10000 0x8 0xd2000000 0x0 0x10000 @@ -1804,7 +1804,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p1_sec_a: crypto@400,d2000000 { + p1_sec_a: crypto@400d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x400 0xd0000000 0x0 0x10000 0x400 0xd2000000 0x0 0x10000 @@ -1845,7 +1845,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p1_sec_b: crypto@408,d2000000 { + p1_sec_b: crypto@408d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x408 0xd0000000 0x0 0x10000 0x408 0xd2000000 0x0 0x10000 -- 2.18.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] arm64: dts: hisilicon hip07: drop commas from @address node names @ 2018-09-12 16:07 ` Jonathan Cameron 0 siblings, 0 replies; 8+ messages in thread From: Jonathan Cameron @ 2018-09-12 16:07 UTC (permalink / raw) To: linux-arm-kernel Reported-by: Rob Herring <robh+dt@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Fixes: e4a1f7858ab8 ("arm64: dts: hisi: add SEC crypto accelerator nodes for hip07 SoC") --- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 28 ++++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index c33adefc3061..bc0113445655 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -949,35 +949,35 @@ reg = <0x0 0xc6000000 0x0 0x40000>; }; - p0_its_dsa_b: interrupt-controller at 8,c6000000 { + p0_its_dsa_b: interrupt-controller at 8c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x8 0xc6000000 0x0 0x40000>; }; - p1_its_peri_a: interrupt-controller at 400,4c000000 { + p1_its_peri_a: interrupt-controller at 4004c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x4c000000 0x0 0x40000>; }; - p1_its_peri_b: interrupt-controller at 400,6c000000 { + p1_its_peri_b: interrupt-controller at 4006c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x6c000000 0x0 0x40000>; }; - p1_its_dsa_a: interrupt-controller at 400,c6000000 { + p1_its_dsa_a: interrupt-controller at 400c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0xc6000000 0x0 0x40000>; }; - p1_its_dsa_b: interrupt-controller at 408,c6000000 { + p1_its_dsa_b: interrupt-controller at 408c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; @@ -1066,7 +1066,7 @@ num-pins = <3>; }; }; - p0_mbigen_alg_b:interrupt-controller at 8,d0080000 { + p0_mbigen_alg_b:interrupt-controller at 8d0080000 { compatible = "hisilicon,mbigen-v2"; reg = <0x8 0xd0080000 0x0 0x10000>; @@ -1083,7 +1083,7 @@ num-pins = <3>; }; }; - p1_mbigen_alg_a:interrupt-controller at 400,d0080000 { + p1_mbigen_alg_a:interrupt-controller at 400d0080000 { compatible = "hisilicon,mbigen-v2"; reg = <0x400 0xd0080000 0x0 0x10000>; @@ -1100,7 +1100,7 @@ num-pins = <3>; }; }; - p1_mbigen_alg_b:interrupt-controller at 408,d0080000 { + p1_mbigen_alg_b:interrupt-controller at 408d0080000 { compatible = "hisilicon,mbigen-v2"; reg = <0x408 0xd0080000 0x0 0x10000>; @@ -1187,7 +1187,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p0_smmu_alg_b: smmu_alg at 8,d0040000 { + p0_smmu_alg_b: smmu_alg at 8d0040000 { compatible = "arm,smmu-v3"; reg = <0x8 0xd0040000 0x0 0x20000>; interrupt-parent = <&p0_mbigen_smmu_alg_b>; @@ -1200,7 +1200,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_a: smmu_alg at 400,d0040000 { + p1_smmu_alg_a: smmu_alg at 400d0040000 { compatible = "arm,smmu-v3"; reg = <0x400 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_a>; @@ -1213,7 +1213,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_b: smmu_alg at 408,d0040000 { + p1_smmu_alg_b: smmu_alg at 408d0040000 { compatible = "arm,smmu-v3"; reg = <0x408 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_b>; @@ -1763,7 +1763,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p0_sec_b: crypto at 8,d2000000 { + p0_sec_b: crypto at 8d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x8 0xd0000000 0x0 0x10000 0x8 0xd2000000 0x0 0x10000 @@ -1804,7 +1804,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p1_sec_a: crypto at 400,d2000000 { + p1_sec_a: crypto at 400d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x400 0xd0000000 0x0 0x10000 0x400 0xd2000000 0x0 0x10000 @@ -1845,7 +1845,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p1_sec_b: crypto at 408,d2000000 { + p1_sec_b: crypto at 408d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x408 0xd0000000 0x0 0x10000 0x408 0xd2000000 0x0 0x10000 -- 2.18.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: crypto: hip07-sec, drop incorrect commas 2018-09-12 16:07 ` Jonathan Cameron @ 2018-09-26 20:36 ` Rob Herring -1 siblings, 0 replies; 8+ messages in thread From: Rob Herring @ 2018-09-26 20:36 UTC (permalink / raw) To: Jonathan Cameron; +Cc: linux-arm-kernel, devicetree, linux-crypto, xuwei On Wed, Sep 12, 2018 at 05:07:17PM +0100, Jonathan Cameron wrote: > There should not be a comma in the address used for the instance > so drop them. > > This is a left over from a review of the final version before > Herbert Xu picked the series up. > > Reported-by: Rob Herring <robh+dt@kernel.org> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Fixes: 8f026dc887fe ("dt-bindings: Add bidnings for Hisilicon SEC crypto accelerators") > --- > .../devicetree/bindings/crypto/hisilicon,hip07-sec.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Applied. The dts change can go thru arm-soc. Rob ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] dt-bindings: crypto: hip07-sec, drop incorrect commas @ 2018-09-26 20:36 ` Rob Herring 0 siblings, 0 replies; 8+ messages in thread From: Rob Herring @ 2018-09-26 20:36 UTC (permalink / raw) To: linux-arm-kernel On Wed, Sep 12, 2018 at 05:07:17PM +0100, Jonathan Cameron wrote: > There should not be a comma in the address used for the instance > so drop them. > > This is a left over from a review of the final version before > Herbert Xu picked the series up. > > Reported-by: Rob Herring <robh+dt@kernel.org> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Fixes: 8f026dc887fe ("dt-bindings: Add bidnings for Hisilicon SEC crypto accelerators") > --- > .../devicetree/bindings/crypto/hisilicon,hip07-sec.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Applied. The dts change can go thru arm-soc. Rob ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-09-26 20:36 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-09-12 16:07 [PATCH 1/2] dt-bindings: crypto: hip07-sec, drop incorrect commas Jonathan Cameron 2018-09-12 16:07 ` Jonathan Cameron 2018-09-12 16:07 ` Jonathan Cameron 2018-09-12 16:07 ` [PATCH 2/2] arm64: dts: hisilicon hip07: drop commas from @address node names Jonathan Cameron 2018-09-12 16:07 ` Jonathan Cameron 2018-09-12 16:07 ` Jonathan Cameron 2018-09-26 20:36 ` [PATCH 1/2] dt-bindings: crypto: hip07-sec, drop incorrect commas Rob Herring 2018-09-26 20:36 ` Rob Herring
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